1. Field of the Invention
Embodiments of the present invention relate to a low profile semiconductor device and method of fabricating same.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate. The substrate may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for connection of the die to a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
A cross-section of a conventional semiconductor package 18 (without molding compound) is shown in
It is known to layer semiconductor die on top of each other either with an offset or in a stacked configuration. In an offset configuration, a die is stacked on top of another die so that the bond pads of the lower die are left exposed. An offset configuration provides an advantage of convenient access of the bond pads on each of the semiconductor die. However, the offset requires a greater footprint on the substrate, where space is at a premium.
In stacked configurations, such as that shown in prior art
There is an ever-present drive to increase storage capacity within memory modules. One method of increasing storage capacity is to increase the number of memory die used within the package. In portable memory packages, the number of die which may be used is limited by the thickness of the package. There is accordingly a keen interest in decreasing the thickness of the contents of a package while increasing memory density. The package 18 shown in
An embodiment of the present invention relates to a low profile semiconductor package including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate layer in which the wire bond loops between the first semiconductor die and substrate are embedded. The intermediate layer may be an electrically insulative epoxy applied as a viscous liquid onto the first semiconductor die. The intermediate layer may be applied over at least substantially the entire surface of the first semiconductor die, or only in discrete quantities over the bond pads of the first semiconductor die.
After the intermediate layer is applied, the second semiconductor die may be stacked on top of the intermediate layer. In accordance with the present invention, a dielectric layer may be formed at the interface between the second semiconductor die and intermediate layer. In embodiments, the dielectric layer may be formed on a back surface of the second semiconductor die by any of a variety of known methods, such as for example laminating an epoxy, or growing or depositing a dielectric film during the fabrication of the semiconductor wafer from which the second semiconductor die is taken. In instances where a wafer is background to bring it to a desired thickness, the dielectric layer can be formed after the backgrind process and prior to assembly onto the first semiconductor die.
As the back side of the second semiconductor die is an electrical insulator, the intermediate layer need not space the wire bond loops from the second semiconductor die as in the prior art, and the apex of bond wires may come into contact with the dielectric layer. The spacing between the first and second stacked semiconductor die may thus be made thinner in comparison to conventional stacked semiconductor die configurations. The second semiconductor die may further be affixed under a compressive load so as to reduce a thickness of the intermediate layer, as well as partially flattening the height of the bond wires above the surface of the first semiconductor die.
Once all semiconductor die are affixed and wire bonded to the substrate, the semiconductor package may be cured, including for example by heating and/or by ultraviolet radiation. In an alternative embodiment, the intermediate layer may be cured before the second semiconductor die is affixed thereto.
Embodiments will now be described with reference to
The present invention will now be described with reference to the flowchart of
Although not critical to the present invention, substrate 102 may be a variety of different chip carrier mediums, including a PCB, a leadframe or a tape automated bonded (TAB) tape. Where substrate 102 is a PCB, the substrate may be formed of a core having top and/or bottom conductive layers formed thereon. The core may be various dielectric materials such as for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like.
The conductive layers may be formed of copper or copper alloys, plated copper or plated copper alloys, Alloy 42 (42FE/58NI), copper plated steel or other metals or materials known for use on substrates. The conductive layers may be etched into a conductance pattern as is known for communicating signals between the semiconductor die and an external device. A dummy pattern may also be provided in the conductive layers as is known to reduce mechanical stresses on the substrate otherwise resulting from uneven thermal expansion within the substrate. Substrate 102 may additionally include exposed metal portions forming contact pads 110 (
After semiconductor die 100 is affixed to substrate 102 in step 200, bond wires 106 may be attached between bond pads 108 (
In step 204, an intermediate layer 120 may be applied onto the exposed surface of die 100. The intermediate layer 120 may for example be an electrically insulative adhesive epoxy of known composition available for example from Nitto Denko Corp. of Japan, Abelstik Co., California or Henkel Corporation, California. The intermediate layer 120 may be applied as a viscous liquid, which remains in that state until cured in a reflow process explained hereinafter. In embodiments, the intermediate layer 120 is applied as a liquid, but has a sufficiently high viscosity to mechanically support a second semiconductor die placed on layer 120 as explained hereinafter. In embodiments, the viscosity may be for example about 1-2×106 centipoise, but it is understood that the viscosity may be higher or lower than that in alternative embodiments. The intermediate layer 120 may be the same as or different from the material used as the adhesive layer 104. In an alternative embodiment, spacer balls may be provided within the intermediate layer 120. The spacer balls may be polymeric spheres that act as spacers between the die 100 and a second die mounted thereon as explained hereinafter. Such spacer balls are known in the art, and are disclosed for example in U.S. Pat. No. 6,650,019, entitled, “Method of Making a Semiconductor Package Including Stacked Semiconductor Die,” which patent is incorporated herein by reference in its entirety.
As seen in
In addition to adhering the stacked semiconductor die together within the package 80, the intermediate layer 120 provides some spacing between the two stacked semiconductor die for location of the wire bond loops 106. However, no additional space in the intermediate layer is required to separate the wire bond loops 106 from a next adjacent semiconductor die. In particular, in the prior art, the adhesive layer in which the bond wires were embedded needed to be thick enough to ensure the bond wires would be prevented from shorting against the bottom surface of the next adjacent die. However, as explained in greater detail hereinafter, a surface of a second die affixed to the intermediate layer 120 is an electrical insulator. Accordingly, intermediate layer 120 need not space wire bond loops 106 from the next adjacent die as in the prior art, and the spacing between the stacked die may be made thinner in comparison to conventional stacked semiconductor die configurations. For example, the intermediate layer 120 may be between 25-50 microns (μm), as compared to about 75 μm in the prior art. It is understood that the thickness of the intermediate layer 120 may be less than 25 μm and greater than 50 μm in alternative embodiments of the present invention.
As indicated above, in step 206, a second semiconductor die 122 may be stacked on top of the intermediate layer 120 as shown in
Once die 122 is affixed onto intermediate layer 120, die 122 may be wire bonded to substrate 102 in a step 210 using bond wires 124 in a known wire bond process.
Embodiments of the present invention may include only the pair of semiconductor die 100 and 122. However, in further embodiments, more than two semiconductor die may be stacked atop each other. In such embodiments, as indicated by the dashed arrow in
As indicated above, intermediate layer 120 is applied with a viscosity sufficient to support semiconductor die 122 without excessively flattening wire bond loops 106. However, when semiconductor die 122 is attached to intermediate layer 120, pressure may be exerted on the intermediate layer so as to reduce the thickness of intermediate layer 120. In so doing, the apex of bond wires 106 may come into contact with dielectric layer 130 as shown in
In a further embodiment shown in
Once all semiconductor die are affixed and wire bonded to substrate 102, the semiconductor package 80 may be cured in a reflow process of step 212 to harden each of the adhesive layers, including intermediate layer 120 and die attach layer 104. Curing may be accomplished by a variety of known methods, depending on the adhesive material used, including for example by heating and/or by ultraviolet radiation.
In the embodiment described above with respect to the flowchart of
In embodiments described above, the intermediate layer 120 may be an adhesive material. However, it is understood that where the dielectric layer 130 is an adhesive, the intermediate layer 120 need not be an adhesive. In such an embodiment, the layer 120 may be applied as a liquid around bond wires 106 and act only as a spacer layer spacing the die 100 and 122 from each other and electrically isolating the bond wires 106 from each other. The die 100 and 122 in such an embodiment would be affixed to each other by the electrically insulative adhesive layer 130.
An alternative embodiment of the present invention is shown in
In this alternative embodiment, as indicated in
Once die 122 is affixed to the die 100 in the embodiment of
In the above-described embodiments, the bond wires from die 100 and 122 may be uncoated gold, though it may alternatively be copper, aluminum or other metals. In a further embodiment of the present invention, the bond wires from die 100 and/or 122 may be pre-insulated (i.e., prior to be immersed in intermediate layer 120) with polymeric insulation that makes the surface of the wire electrically non-conductive. Such pre-insulated bond wire is known for preventing shorting between adjacent bond wires. Two examples of a pre-insulated bond wire which is suitable for use in the present invention are disclosed in U.S. Pat. No. 5,396,104, entitled, “Resin Coated Bonding Wire, Method of Manufacturing the Same, and Semiconductor Device,” and U.S. Published Patent Application No. 2004/0124545, entitled, “High Density Integrated Circuits and the Method of Packaging the Same,” both of which are incorporated by reference herein in their entirety. An embodiment utilizing a pre-insulated bond wire may operate with or without intermediate layer 120. In such an embodiment operating without intermediate layer 120, the dielectric layer 130 may be an adhesive for affixing the die together.
As shown in
In embodiments, the semiconductor die described above may include one or more flash memory chips, and possibly a controller such as an ASIC, so that the package 160 may be used as a flash memory device. It is understood that the package 160 may include semiconductor die configured to perform other functions in further embodiments of the present invention.
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.