Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor

Abstract

Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides integrated circuitry including a monolithic semiconductive substrate; a power semiconductor switching device comprising a plurality of field effect transistors formed using the monolithic semiconductive substrate and having a plurality of electrical contacts including a plurality of gate contacts, a plurality of source contacts coupled in parallel and a plurality of drain contacts coupled in parallel; and auxiliary circuitry formed using the monolithic semiconductive substrate and configured to couple with at least one of the electrical contacts of the power field effect transistors

Description

TECHNICAL FIELD

[0003] This invention relates to power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor.

BACKGROUND OF THE INVENTION

[0004] Computational power of digital processing circuitry is related to the conversion of input DC power to waste heat. As digital computational powers increase, the associated power consumption and heat generated by processing devices also increase. Power supply voltages of logic circuits have been reduced from 5 Volts to 1.2 Volts or less to alleviate excessive generation of heat and power consumption. However, reduction of power supply voltages has complicated other issues of power supply and distribution to logic circuits. For example, electrical resistance between power supplies and logic circuits has a more significant impact upon efficiency as supply voltages continued to be reduced.

[0005] Some designs have provided power to PC boards at high voltages (e.g., 48 Volts) and then utilize on-board converters to convert the received high voltage energy to 1.2 Volt or other low voltage supply energy for application to logic circuits. To minimize the size of such converters, the stored energy requirements in the magnetics and capacitors can be reduced by increasing the switching frequency of the converter. However, conventional power semiconductor configurations utilized in converters and capable of handling relatively large currents can not typically switch efficiently at the desired switching speeds.

[0006] FIG. 1 depicts a conventional vertical geometry power MOSFET device having a plurality of n+ source contact regions 3 which lie within p (body) regions 3P (typically formed as hexagonal islands), where both the p (body) regions 3P and the n+ source contact regions 3 are electrically connected to the upper source contact metal 3M. The gate conductors 2 are insulated from source contact metal 3M under which they lie by the insulator 31 and from the silicon substrate by the thin gate insulator 21. The gate conductors 2 cover the regions between the p (body) regions 3P, extending across the edge (surface channel) portion of the perimeter of the p (body) regions 3P to the n+ source regions 3. When the gate conductors 2 are biased more positively than the threshold voltage of this conventional n-channel power MOSFET, electron flow through these surface channel regions is induced which results in electron flow along indicated paths 4. Electron paths 4 are formed from the adjacent n+ source regions 3 horizontally through the surface channel, vertically through the n− drain drift region 5N to the n+ drain region 5 to the bottom drain metallization contact 6 shown in FIG. 1. This current flow path leads to values of source-drain ON resistance that are higher than desired for efficient low voltage power conversion applications.

[0007] The equivalent circuit of a conventional power MOSFET illustrated in FIG. 1 is depicted in FIG. 2. A p-n body diode 7 is provided from the source 3 to the drain 6 and comprises the p body region 3P and the n− and n+ drain regions 5N and 5 shown in FIG. 1. The body diode 7 is a relatively large p-n−-n+ diode with a very large diffusion charge storage capacity Qd. Accordingly, when the body diode 7 is first reversed biased after heavy forward conduction, a large transient reverse current ir flows for a substantial period of time tr=Qd/ir which can limit usable switching frequencies.

[0008] There exists needs for improved semiconductor devices and methodologies which overcome problems associated with conventional arrangements.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of necessary fees.

[0010] Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

[0011] FIG. 1 is a cross-sectional view of a conventional vertical power MOSFET device.

[0012] FIG. 2 is a schematic representation of the conventional power MOSFET equivalent circuit.

[0013] FIG. 3 is schematic illustration of an exemplary synchronous rectification power converter.

[0014] FIG. 4 is an illustrative representation of exemplary components formed upon a monolithic semiconductor die.

[0015] FIG. 5 is a side cross-sectional view of an exemplary high-current, low resistance area interconnect die package assembly.

[0016] FIG. 6 is another (top) cross-sectional view of the high-current, low resistance area interconnect die package assembly of FIG. 5.

[0017] FIG. 7 is a cross-sectional view of an alternative high-current, low resistance area interconnect die package assembly.

[0018] FIG. 8 is a detailed cross-sectional view of the package and a planar high-current silicon switch die of FIG. 5 or FIG. 7.

[0019] FIG. 8A is another cross-sectional view of a portion of the integrated circuit assembly of FIG. 8.

[0020] FIG. 9 is a cross-sectional view of another alternative exemplary configuration of an integrated circuit assembly.

[0021] FIG. 10 is a plan view of an exemplary semiconductor die provided in a flip-chip arrangement.

[0022] FIG. 11 is a side view of an exemplary integrated circuit assembly including the integrated circuit die of FIG. 10.

[0023] FIG. 12 is another side view of the integrated circuit assembly shown in FIG. 11.

[0024] FIG. 13 is an illustrative representation depicting a plurality of exemplary planar MOSFET devices of a power semiconductor switching device.

[0025] FIG. 14 is a plan view of an exemplary arrangement of the planar MOSFET transistors of FIG. 13 fabricated within a semiconductor die.

[0026] FIG. 15 is a schematic representation of an exemplary gate driver amplifier coupled with the power semiconductor switching device.

[0027] FIG. 16 is a schematic representation of an exemplary active diode p-channel MOSFET coupled with the power semiconductor switching device.

[0028] FIG. 17 is a graphical representation depicting drain currents versus a plurality of drain-source voltages of an exemplary power semiconductor switching device.

[0029] FIG. 18 is another graphical representation depicting drain currents versus additional drain-source voltages of the exemplary power semiconductor switching device graphed in FIG. 17.

[0030] FIG. 19 is yet another graphical representation depicting drain currents versus drain-source voltages of the exemplary power semiconductor switching device graphed in FIG. 17 and FIG. 18.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

[0032] Like reference numerals represent like components with differences therebetween being represented by a convenient suffix, such as “a”.

[0033] Referring to FIG. 3, a switching power converter 10 is depicted according to exemplary aspects of the present invention. The switching power converter 10 illustrated in FIG. 3 is configured as a synchronous rectification power converter. Other configurations of power converter 10 are possible. The illustrated embodiment of power converter 10 includes a transformer 12 comprising a primary side 14 and a secondary side 16. Power converter 10 is configured to implement DC to DC power conversion operations. High-current, low “on” resistance planar MOSFET power semiconductor switching devices illustrated as reference 50 provided according to aspects of the present invention are included on the secondary side 16 of power converter 10 in the depicted embodiment. In a conventional diode rectified power converter, the switches 50 would be replaced by a pair of Schottky diode rectifiers with their anodes grounded.

[0034] Primary side 14 comprises a center-tapped primary transformer winding 20 coupled with plural primary switching devices 22, 24 and primary terminals 26. Switching devices 22, 24 are implemented intermediate one of primary terminals 26 and primary transformer winding 20.

[0035] Secondary side 16 includes a center-tapped secondary transformer winding 30 coupled with a plurality of secondary switches 32, 34 and secondary terminals 36. Primary side 14 receives electricity via terminals 26 at a first voltage and a first current in one implementation of power converter 10. Secondary transformer winding 30 is coupled with primary transformer winding 20 and is configured to provide electricity at a second voltage different than the first voltage and a second current different than the first current to terminals 36. For example, in the depicted exemplary embodiment, primary side 14 is configured to receive electricity at a first voltage greater than the voltage provided upon secondary side 16. In addition, primary side 14 receives current having a magnitude less than the magnitude of current provided at terminals 36.

[0036] In one exemplary application, power converter 10 is implemented to provide electricity to an associated microprocessor and/or other processing device(s) in a low voltage application (e.g., 1.2 Volts, 2.5 Volts) wherein utilization of diodes, for example in a diode rectification power converter, is rendered inefficient by the excessive voltage drops across the diode rectifier switching devices. For example, power converter 10 may be utilized in a personal computer, server, work station or other processing and logic circuitry applications, including low voltage, high current applications.

[0037] As shown, a controller 38 is provided coupled with primary switches 22, 24, secondary switches 32, 34 and secondary terminals 36. Controller 38 is configured to monitor output voltage and current via secondary terminals 36 to control operations of power converter 10. For example, controller 38 controls the timing of switching operations of primary switches 22, 24 and secondary switches 32, 34 to implement appropriate power conversion operations and to maintain the voltage and current of electricity within secondary side 16 in a desired range.

[0038] As described in detail below, secondary switches 32, 34 are configured to withstand power currents. Exemplary power currents include currents experienced within power devices which are greater than typical signaling currents which are usually a few tens of milliamps. Exemplary power currents are greater than one Ampere and reach magnitudes of 100 Amperes-200 Amperes or greater in exemplary configurations. Secondary switches 32, 34 are implemented as power semiconductor switching devices 50 described herein according to additional aspects of the invention. Such devices 50 may be configured to accommodate currents approaching or exceeding 1000 Amperes in exemplary configurations.

[0039] Power semiconductor switching devices 50 comprise high current devices having ultra low ON resistance values (Ron) in exemplary configurations. Utilizing power semiconductor switching devices 50 described herein, Ron values less than 0.00015 Ohms are possible for configurations capable of handling 200 Amperes. Accordingly, it is favorable to use the low voltage, high current power devices 50 as secondary switches 32, 34 having low Ron values for improved efficiency.

[0040] In the depicted power converter applications, controller 38 is configured to sense output voltages and currents at terminals 36. Responsive to such monitoring, controller 38 applies control signals to primary switches 22, 24 and secondary switches 32, 34 to control the operation of the switches to maintain the voltages and currents at terminals 36 within a desired range. As illustrated, controller 38 applies control signals to the gates of secondary switches 32, 34 implemented as power semiconductor switching devices 50 according to exemplary aspects of the invention.

[0041] Referring to FIG. 4, an exemplary configuration of secondary switches 32, 34 configured as power semiconductor switching devices 50 according to aspects of the present invention is illustrated. Power semiconductor switching devices 50 individually comprise a power MOSFET transistor which may be formed by a plurality of MOSFET transistors coupled in parallel according to additional aspects of the invention. One common control signal is utilized to control the individual MOSFET transistors of the power device 50. Exemplary MOSFET transistors utilized to form an individual one of the power semiconductor switching devices 50 are described below as reference 174 in FIG. 13 and FIG. 14. Such transistors are implemented as planar, horizontally configured n-channel MOSFET devices in one exemplary aspect.

[0042] FIG. 4 depicts a monolithic semiconductor die 52 containing plural power semiconductor switching devices 50 according to one embodiment. The semiconductor die 52 is fabricated from a monolithic semiconductive substrate 56 in the described exemplary embodiment. For example, semiconductor die 52 is formed from a semiconductive wafer (not shown) such as silicon, silicon carbide, gallium arsenide or other appropriate semiconductive substrate.

[0043] In the described embodiment, portions of semiconductive substrate 56 are doped with a p-type dopant providing a p-substrate or p-well. In addition, an n-well may also be formed within semiconductive substrate 56. As described further below, n-channel MOSFET devices are formed within portions of substrate 56 comprising p-type portions or wells of substrate 56 and p-channel MOSFET devices are formed within n-type portions or wells of substrate 56. P-type and n-type portions of substrate 56 are shown in FIG. 13 for example.

[0044] The depicted monolithic semiconductor die 52 also comprises auxiliary circuitry 54 according to aspects of the present invention. Auxiliary circuitry 54 is circuitry apart from circuitry comprising power semiconductor switching devices 50. In some applications, auxiliary circuitry 54 is coupled with and favorably utilized in conjunction with power devices 50. For example, auxiliary circuitry 54 comprises controller circuitry or driver circuitry to control power semiconductor switching devices 50. In other applications, auxiliary circuitry 54 is not coupled with and is unrelated to operations of power semiconductor switching devices 50. In some configurations, auxiliary circuitry 54 is implemented as application specific integrated circuitry (ASIC).

[0045] The depicted semiconductor die 52 is illustrated with respect to the power converter 10 application of FIG. 3. Other configurations of semiconductor die 52 including other arrangements of power semiconductor switching devices 50 and auxiliary circuitry 54 configured for other applications are possible. In the illustrated exemplary configuration, auxiliary circuitry 54 formed upon monolithic semiconductor die 52 and comprising controller 38 and gate amplifiers 60 are configured to couple with at least one of the electrical contacts (i.e., gate contact in the arrangement of FIG. 4) of the respective power semiconductor switching devices 50.

[0046] Regardless of the application of die 52 or power devices 50, aspects of the present invention provide auxiliary circuitry 54 upon monolithic semiconductor die 52 including power semiconductor switching devices 50. Fabrication of power semiconductor switching devices 50 using common CMOS processing methodologies according to aspects of the present invention or other processing techniques facilitates formation of auxiliary circuitry 54 using similar processing methodologies upon monolithic semiconductor die 52. For example, if CMOS processes are used to form devices 50, such CMOS processes can also be utilized to form auxiliary circuitry 54, if desired. Power semiconductor switching devices 50 may be fabricated simultaneously with auxiliary circuitry 54 in such arrangements. The capability to provide auxiliary circuitry 54 upon the semiconductor die 52 is enabled by the fabrication of power semiconductor switching devices 50 comprising planar MOSFET devices according to aspects of the present invention which may be fabricated within a standard CMOS foundry ordinarily used to fabricate small-signal digital or analog circuits.

[0047] Apart from the illustrated fabrication efficiencies of power semiconductor switching devices 50 and auxiliary circuitry 54, there may be other reasons to provide auxiliary circuitry 54 upon the same semiconductor die 52 as devices 50. For example, and as described further below, exemplary configurations of power semiconductor switching devices 50 individually comprise a plurality of MOSFETs, including for example, thousands of parallel-coupled MOSFETs (a plurality of MOSFET switching devices of individual power devices 50 are depicted in exemplary configurations in FIG. 13 and FIG. 14). Provision of auxiliary circuitry 54 including control circuitry and driver circuitry upon the same die 52 as devices 50 advantageously facilitates driving the gate capacitances of the individual MOSFETs comprising power devices 50 and minimizes the capacitance which must be driven by external control circuitry such as the outputs from the converter controller 38. Further details regarding driving gate capacitances of devices 50 are described below and other advantages may be gained by providing auxiliary circuitry 54 upon monolithic substrate 56.

[0048] In particular, it may be desired to provide converter controller 38 adjacent to the secondary side 16 in synchronous rectifier switching applications. According to embodiments described herein, auxiliary circuitry 54 is configured as converter controller 38 provided upon die 52 including power devices 50. Providing controller 38 adjacent to devices 50 is advantageous to significantly reduce parts count in providing power converter products. Controller circuitry 38 may be implemented using analog or digital control circuit configurations.

[0049] As mentioned above, power converter controller 38 provides respective control signals to control the operation of secondary switches 32, 34 implemented as power semiconductor switching devices 50 upon die 52 according to aspects of the present invention. Controller 38 is also configured to apply control signals externally of semiconductor die 52. For example, controller 38 is arranged in the exemplary configuration to apply control signals (Phip1, Phip2) to primary switches 22, 24 to control switches 22, 24, generally through some type of isolation device to enable isolation between the input side 14 and output side 16 grounds of power converter 10. Power controller 38 is also coupled with output terminals 36 to sense voltages and currents within the secondary side 16 of power converter 10. Bond pads (not shown) are provided upon semiconductor die 52 to provide coupling of die 52 with external circuitry including terminals 36 and isolation devices coupling to primary switches 22, 24.

[0050] As discussed above, auxiliary circuitry 54 further includes gate driver amplifier circuits 60 coupled intermediate controller 38 and respective power semiconductor switching devices 50. Gate driver amplifier circuits 60 operate to improve power conversion operations or other operations requiring controlled switching of power semiconductor devices 50. Further details regarding an exemplary configuration of amplifiers 60 are discussed below in FIG. 15 as reference 180.

[0051] As mentioned above and according to aspects of the invention, power semiconductor switching devices 50 may be individually implemented as a plurality of parallel-coupled MOSFETs including parallel-coupled gates, parallel-coupled sources and parallel-coupled drains. Gate driver amplifier circuits 60 are configured to provide respective control signals to the parallel-coupled gates of the MOSFETs of power semiconductor switching devices 50. Depending upon the application of power devices 50 (e.g., application within power converter 10) significant input currents may be required to drive the MOSFET gates of individual power semiconductor switching devices 50. Utilization of gate driver amplifiers 60 according to aspects of the invention facilitates driving these input currents and minimizes the capacitance which must be driven by the control circuitry controlling the gates of power semiconductor switching devices 50 providing improved switching speeds.

[0052] Further, large current spikes involved in charging and discharging gate capacitance of power semiconductor switching devices 50 comprising numerous parallel-coupled MOSFETs places demands on available current and provides a serious limitation to timing precision and practical switching speeds. In some configurations, (e.g., some configurations of power semiconductor switching devices 50 comprise 500,000 MOSFET devices or more arranged in parallel as described below) 20 nF gate capacitances are driven. The utilization of gate driver amplifiers 60 upon semiconductor die 52 reduces the capacitance at the gate control input to the gate drive amplifiers 60 to 4.5 pF of a 500,000 MOSFET device 50 which may be easily controlled directly from digital timing circuits such as controller 38 to precisions of a few nanoseconds.

[0053] Alternative auxiliary circuitry 54 includes zero-current switching/timing circuitry to detect the absence of currents within secondary inductive device 30. Zero-current switching/timing circuitry may be utilized to determine proper moments in time for controlling switching of secondary switches 32, 34.

[0054] According to additional aspects, auxiliary circuitry 54 includes load protection circuitry configured to detect voltage overage conditions and current overage conditions. Controller 38 coupled with appropriate load protection circuitry controls operation of power semiconductor switching devices 50 responsive thereto, including opening or closing appropriate switching devices 22, 24, 32, 34.

[0055] According to additional aspects, auxiliary circuitry 54 includes protection circuitry configured to detect drain-source or gate-source voltage overage conditions within devices 50 which could potentially be damaging to the devices and to institute corrective action such as to mitigate the over voltage conditions. Implementation of this function requires coupling from the drains of the power semiconductor switching devices 50 through some type of internal or external voltage discrimination elements (such as a Zener diodes or transient voltage suppression (TVS) circuitry) back to either auxiliary inputs on the respective gate drive amplifiers 60 or to the controller 38 (FIG. 3). When the voltage discrimination element provides feedback that a dangerous overvoltage condition exists at the drain of one of power MOSFET devices 32 or 34, the protection circuitry functions to generate a gate voltage on that device such as to cause a momentary drain current pulse capable of suppressing the overvoltage condition in the manner of an active snubber circuit.

[0056] Exemplary configurations of zero-current switching/timing circuitry, load protection circuitry, active snubber circuitry or other configurations of auxiliary circuitry 54 are implemented as application specific integrated circuitry (ASIC) as mentioned above.

[0057] The depicted exemplary configuration of device 50 within semiconductor die 52 is provided for discussion purposes with respect to the exemplary power converter 10 application. Other configurations are possible including provision of a single power semiconductor switching device 50, additional power semiconductor switching devices 50 and/or other associated auxiliary circuitry 54 upon an appropriate semiconductor die 52. Other power conversion configurations and other applications of power semiconductor switching devices 50 described herein are possible. Power semiconductor switching devices 50 are usable in other low voltage, high current applications apart from exemplary applications described herein.

[0058] Aspects of the present invention also provide devices and methods for packaging of power semiconductor switching devices 50 and semiconductor die 52 including devices 50. As set forth above, devices 50 according to exemplary configurations comprise plural MOSFET devices coupled in parallel. Examples of such MOSFETs are depicted in FIG. 13 and FIG. 14 as planar, horizontally configured MOSFETs having high-current power electrodes (e.g., source and drain) provided adjacent on a common surface as opposed to conventional power MOSFETs wherein the source is provided upon an upper surface and the drain is provided upon an opposing lower surface, as illustrated in FIG. 1.

[0059] Various exemplary packaging configurations and integrated circuit assemblies according to aspects of the present invention are described hereafter with reference to FIG. 5-FIG. 12. The illustrated configurations are exemplary and other packaging or assembly arrangements are possible for power semiconductor switching devices 50, including other combinations of the various layers and electrical connections depicted in FIG. 5-FIG. 12.

[0060] Referring to FIG. 5 and FIG. 6, a first exemplary integrated circuit assembly 70 is shown. Integrated circuit assembly 70 includes semiconductor die 52 including one or more power semiconductor switching device 50 and auxiliary circuitry 54 (if circuitry 54 is provided within die 52). In the illustrated example, semiconductor die 52 is implemented in a flip chip configuration. Other packaging designs of semiconductor die 52 are possible.

[0061] Integrated circuit assembly 70 further includes a package 73 coupled with semiconductor die 52. Package 73 comprises one or more intermediate layer 74, a source plane 76, and a drain plane 78 (plural layers 74, 74a are illustrated in the exemplary package configuration of FIG. 5 and one intermediate layer is shown in the exemplary arrangement of FIG. 3 in Appendix A).

[0062] Intermediate layer(s) 74 comprise “fineline” layer(s) in the illustrated exemplary embodiment. For example, intermediate layer(s) 74 are implemented as plated copper planes (5-10 microns typical). Intermediate layer(s) 74 are capable of being patterned to horizontal feature sizes sufficiently small as to allow area array contact to the semiconductor die 52. Intermediate layer(s) 74 which provide electrical conduction in a horizontal direction may be referred to as horizontal interconnect layers.

[0063] In one exemplary embodiment, drain plane 78 is implemented as a plated copper plane (0.010 inches or 250 microns typical) and plane 76 is implemented as a source plane comprising copper-invar-copper (0.030 inches or 750 microns typical). Other configurations of layer(s) 74 and planes 76, 78 are possible.

[0064] For example, the drain plane 78 may be divided into two or more portions in an exemplary alternative configuration wherein individual portions service respective portions (e.g., halves) of the area of die 52 and coupled with two separate drain contact areas. In such an arrangement, a die containing two power devices 50 as illustrated in FIG. 4 could be accommodated (whereas the illustration of FIG. 5 and FIG. 6 shows only a single high-current drain contact 82, along with the single high-current source contact 80, suitable for a die 52 having a single power device 50 in the depicted exemplary configuration).

[0065] In addition, the integrated circuit assembly 70 includes a single terminal source contact 80 and a single terminal drain contact 82 in the depicted exemplary configuration. Opposing ends of planes 76, 78 define terminal contacts 80, 82 in the exemplary configuration. Terminal contacts 80, 82 are configured to couple with devices external of assembly 70 upon installation of assembly 70 into final products (e.g., terminal contacts 80, 82 couple with a motherboard in an exemplary computer application).

[0066] Referring to FIG. 6, one or more gate lead replaces a drain solder ball in the array to provide connectivity to the gate of device 50. The package lead which attaches to the gate may be fabricated in layer 74 if the gate ball is at the perimeter. FIG. 6 depicts further details of the package 73 of FIG. 5 looking downward through a cross-sectional line passing through intermediate layer 74a. Die 52 and gate contact 89 fabricated using layer 74 are shown in FIG. 6 for illustrative purposes.

[0067] A plurality of electrical interconnects 84 are depicted which couple intermediate semiconductor die 52 and intermediate layer 74 of package 73. Exemplary electrical interconnects 84 include respective gate, source and drain solder balls 87 coupled with respective mating pads fabricated in intermediate layer 74 in one exemplary configuration. Intermediate layer 74 also provides contact to the gate (as mentioned above) and other lower current connections to the semiconductor die 52 as well as providing external package connection pads for coupling these to a circuit board through suitable connections and can form, in conjunction with solder balls 87 and intermediate layer 74a if desired, the electrical connection between lower current connections of die 52 and their respective external package pads. Electrical interconnects 84 coupled with respective source, drain, gate and other bond pads of semiconductor die 52 (not shown) provide connectivity of such bond pads to intermediate layer 74.

[0068] As shown in the depicted embodiment, intermediate layer 74a is spaced from semiconductor die 52 including power semiconductor switching devices 50 therein. Intermediate layer 74a provides proper coupling of source bond pads of semiconductor die 52 with source plane 76 and permits coupling of drain bond pads of semiconductor die 52 with drain plane 78.

[0069] Intermediate layer 74a is generally implemented as a source plane in the described embodiment. Layer 74a is coupled with source plane 76 and source terminal contact 80 using a plurality of via conductors 90 within vias 88 passing through, but insulated from, drain plane 78. Via conductors 90 provide connectivity of source plane 76 with the proper associated source electrical interconnects 84 and source portions of intermediate layer 74a.

[0070] As shown, layer 74a includes a plurality of vias 86. Portions 77 of layer 74a within vias 86 and electrically insulated from the remainder of layer 74a provide connectivity of respective drain bond pads of die 52 to drain plane 78. Portions of layer 74a within vias 86 provide lateral, horizontal matching of drain bond pads and respective drain interconnects 84 to drain plane 78 as shown illustrating layer 74a as a horizontal interconnect layer.

[0071] Electrical interconnects 84 couple source bond and drain pads of semiconductor die 52 with respective portions of layer 74 in the depicted embodiment. Although not illustrated, an appropriate insulative dielectric material may be provided within vias 86, 88, intermediate source plane 76 and drain plane 78, and intermediate source and drain portions of layer 74a. Further, dielectric material may provided at other desired locations to provide appropriate electrical insulation, such as between planes 76 and 78, between plane 78 and layer 74a, and between layers 74 and 74a. Insulative underfill material may also be provided beneath semiconductor die 52 to protect solder balls 87 and semiconductor die 52.

[0072] As illustrated, FIG. 5 and FIG. 6 depict an exemplary integrated circuitry assembly 70 comprising an area array bumped flip-chip configuration of die 52 mounted to a fineline augmented package 73. The high density solder bump array may be provided directly upon die pads of semiconductor die 52 and contact a mating high density pad array patterned in layer 74 over layer 74a of package 73.

[0073] Package metallization layers thick enough to handle some high source and drain currents can not be patterned fine enough to directly mate to some chip solder bump pitches. Accordingly, in some embodiments, one or more intermediate layer (comprising fineline additive copper/polymer interconnect layers in one embodiment as mentioned above) is implemented to provide an exemplary solution to feature size mismatch of semiconductor die 52 and package 73.

[0074] The intermediate layers are implemented to include pattern plated copper conductor layers with patterned benzocyclobutene (BCB) sold under the trademark CYCLOTENE available from the Dow Chemical Company, and comprising appropriate dielectric layers in one exemplary embodiment. Other patternable dielectric materials such as polyimide could also be used as an alternative to BCB. The described exemplary intermediate layer 74 is capable of being patterned with requisite area bump array feature sizes which are thicker than on-chip metal layers (e.g., typically 5-20 microns of copper compared to 0.4-0.8 microns of aluminum upon a CMOS die). However, such are not as thick as 10 mils (254 microns) or more of copper upon main packaging layers implemented as planes 76, 78 in the described embodiment where undivided source and drain currents pass from the package contacts. Further details regarding similar or alternative configurations of package 73 are illustrated below and in FIG. 6A and FIG. 6B of the Appendix and described in the associated text thereof.

[0075] Referring to FIG. 7, an alternative configuration of integrated circuit assembly is illustrated as reference 70a. Integrated circuit assembly 70a may be utilized in applications having finer solder ball pitch compared to assembly 70. Integrated circuit assembly 70a includes package 73a including a plurality of intermediate layers depicted as references 74b, 74c. Plural intermediate layers 74b, 74pc comprising fineline layers for example and configured as horizontal interconnect layers as shown provide additional flexibility in accommodating feature size mismatch of semiconductor die 52 and package 73a. Additional horizontal interconnect layers for example implemented as additional intermediate layers are utilized in other embodiments if desired to couple additional source and drain bond pads of the semiconductor die 52 with an associated package. Alternatively, in other configurations, the packages are provided with no horizontal interconnect layers and source and drain pads of semiconductor die 52 are coupled with respective source and drain planes 76, 78 using appropriate via conductors 90 or other appropriate configurations.

[0076] Layers 74b, 74c configured as horizontal interconnect layers provide proper connectivity of source and drain electrical interconnects 84a implemented as solder balls 87 with the respective appropriate planes 76, 78a. Layer 74b provides lateral, horizontal alignment for drain connections while layer 74c provides lateral, horizontal alignment for source connections.

[0077] Via conductors 90 provide electrical coupling of appropriate portions of layer 74c with source plane 76. The number of via conductors 90 and vias 88 may be varied according to magnitude of currents to be conducted. Although not shown in FIG. 7, appropriate insulative material is provided in assembly 70a to effectively insulate source and drain conductors of die 52 and package 73a.

[0078] The integrated circuit assemblies depicted herein minimize resistance intermediate source and drain terminal contacts 80, 82. In the exemplary configuration of FIGS. 5 and 6, for example, a total (source+drain) package resistance of approximately 0.0001 Ohms is observed between source and drain terminals 80, 82 in a configuration having a 4 mm×4 mm square semiconductor die 52 having a total of 256 solder balls on a 250 micron pitch (in accordance with the geometry shown in FIGS. 6A and 6B of Appendix A) of a device 50 implemented as a planar MOSFET and comprised of 500,000 MOSFET devices coupled in parallel capable of conducting currents of approximately 200 Amperes. If a finer solder bump pitch, such as 1600 solder balls on a 100 micron pitch were used with the same sized semiconductor die 52 using a finer package contact array pitch as illustrated in FIG. 7 but with the same thicknesses of intermediate layer(s) 74 and planes 76, 78 cited in conjunction with FIGS. 5 and 6, the calculated total (source+drain) package resistance is approximately 0.00008 Ohms. (As shown in FIG. 10 of Appendix A, the modest 23% calculated reduction in package resistance from 103 microOhms to 80 microOhms by going from 256 to 1600 solder balls is accompanied by a calculated reduction in on-chip metallization [the resistance of the metallization layers on the semiconductor die 52] resistance by a factor of 3.7 from 111 microOhms to 30 microOhms).

[0079] FIG. 8 and FIG. 9 depict cross-sectional views of exemplary assemblies for power semiconductor switching devices 50 capable of conducting currents in excess of 200 Amperes and comprising approximately 500,000 planar switching MOSFET devices 174 coupled in parallel (only three n-channel devices 174 are shown in each of FIG. 8 and FIG. 9, while FIG. 8A shows an end view of 8 of these n-channel devices). The assembly 70 of FIG. 8 generally corresponds to the assembly depicted in FIG. 5 and FIG. 6. Further details of similar or alternative constructions of FIG. 8 are illustrated as FIG. 3 in the Appendix and described in the associated text therein. Further details of assembly 70b of FIG. 9 are illustrated in FIG. 7 of the Appendix and described in the associated text therein.

[0080] Referring to FIG. 8, details of an exemplary 5-layer IC metallization system 100 are depicted upon a CMOS semiconductor die 52. The illustrated metallization 100 may be utilized within the assemblies 70, 70a, 70b, 70c and in conjunction with packages 73, 73a, 73b, 73c (or other assembly and package configurations) although the metallization 100 of FIG. 8 is depicted with reference to assembly 70 and package 73. FIG. 8 depicts a cross-sectional view through planar MOSFET channel stripes and source and drain buss bar stripes of metallization 100 looking in an “X” direction. The depicted semiconductor die 52 includes a plurality of source\drain regions 101 and gate regions 102 therebetween to form plural MOSFETs 174. Source\drain regions 101 and gate regions 102 are preferably implemented as silicide regions, comprising polysilicide for example, formed adjacent to a surface 57 of substrate 56.

[0081] Semiconductor die 52 is coupled with an exemplary package 73. Electrical interconnects 84 comprise solder balls 87 having a bump pitch of 50-250 microns utilizing normal or fine bump pitch technology in exemplary configurations providing connectivity of die 52 and package 73. Further, an intermediate layer 74a is also depicted within package 73.

[0082] Metallization 100 includes plural metal layers including a first metal layer 110, a second metal layer 111, a third metal layer 112, a fourth metal layer 113 and a fifth metal layer 114 elevationally above surface 57 of semiconductive substrate 56. First metal layer 110 depicts source and drain “Y” stripes having dimensions of approximately 25 microns by 0.75 microns. Second metal layer 111 depicts source and drain “X” buss bars having dimensions of approximately 12 microns while portions corresponding to gate 102 have a dimension of 2.5 microns. Third metal layer 112 depicts a source plane with drain holes having dimensions of approximately 3 microns by 3 microns. Fourth metal layer 113 depicts a drain plane having source holes having dimensions of approximately 3 microns by 3 microns. Fifth metal layer 114 depicts a source and drain checkerboard configuration with ball pads comprising source pads 116 and drain pads 118.

[0083] Further details of metallization 100 of a 200 Ampere NMOS switching power transistor are discussed in the Appendix. Details of an exemplary metal layer 110 are discussed in the Appendix with reference to FIG. 4B and the associated text thereof. Further details of an exemplary metal layer 111 are discussed in the Appendix with reference to FIG. 4C and the associated text thereof. Further details of an exemplary metal layer 112 are discussed in the Appendix with reference to FIG. 4D and FIG. 5A and the associated text thereof. Further details of an exemplary metal layer 113 are discussed in the Appendix with reference to FIG. 5B and the associated text thereof. Further details of an exemplary metal layer 114 are discussed in the Appendix with reference to FIG. 5C and FIG. 5D and the associated text thereof.

[0084] The illustrated intermediate layer 74 comprising a fineline plated copper layer provides package solder bump drain and source contact pads 122. In the illustrated embodiment, layer 74 is spaced from substrate 56 comprising one or more power semiconductor switching device 50. As described previously, this space may be filled with insulative underfill material.

[0085] FIG. 8A depicts an illustrative representation of first and second metal layers 110, 111 looking in “Y” direction while FIG. 8 and FIG. 9 look in an “X” direction. Portion 117 of layer 111 comprises a drain buss bar while portion 119 of layer 111 comprises a source buss bar.

[0086] In an alternative embodiment to that illustrated in FIGS. 5, 6, 7 and 8, the intermediate layers may be fabricated on the semiconductor die 52a instead of within the package 73. Referring to FIG. 9, an alternative assembly 70b and package 73b are shown. Plural intermediate layers 74d, 74e are depicted formed upon semiconductor die 52a and metallization 100 including layers 110, 111, 112, 113 and 114a. Layer 74d comprises portions electrically coupled with respective source bond pads 116 and drain bond pads 118 of metallization 114a. In FIG. 9 the area density or pitch of electrical couplings between the semiconductor die metallization 114a and the layer 74d need not be limited to the solder bump density, which allows much higher area array pad 116, 118 densities to be utilized (e.g., pad pitches of 40 microns or smaller, or 10,000 or more on a 4 mm×4 mm semiconductor die 52a), which substantially reduces the contribution of on-chip metallization 100 resistance to the overall chip plus package Ron. The tight mechanical coupling in FIG. 9 between the layers 74d, 74e and/or their associated dielectric layers 124a, 124 with the chip metallization 100 over substantially the complete area of the semiconductor die 52a in one possible embodiment is anticipated to offer improved robustness and potentially improved reliability overthe fine-pitch solder bump approach of FIG. 7 or FIGS. 5, 6 and 8. BCB inter-layer dielectric 124 provides electrical insulation of source and drain electrical connections. Other patternable dielectric materials such as polyimide could be used here in place of BCB. Layer 74e comprises integrated circuit source bond pads 130 and drain bond pads 132 coupled with respective portions of layer 74d. Solder balls 87 are coupled with respective source bond pads 130 and drain bond pads 132. Solder balls 87 are additionally coupled with source solder pads 134 and drain solder pads 136 of an external package to provide electrical connectivity to the external package (only portions of one pair of pads 130, 132 and one pair of pads 134, 136 are shown in FIG. 9). Exemplary external packages include source and drain planes 76, 78 coupled with source and drain terminal contacts 80, 82 as described previously, or the package configuration 73c shown in FIG. 11. Other package configurations are possible which will, in their structure, incorporate pads 134, 136.

[0087] In an exemplary embodiment, fineline copper/polymer intermediate layers 74d, 74e are added to a completed or semi-fabricated semiconductor die 52a in a full-wafer process according to exemplary aspects of the present invention. Because of the very low sheet resistance of the fineline copper planes 74d and 74e, relatively coarse pitches may be utilized in joining the semiconductor die 52 to relatively heavy package metallization features without compromising ON resistance values (Ron). Such permits mating of semiconductor die 52 to relatively simple and commercially available packages using coarse-pitch solder bump, solder patch or other joining technologies.

[0088] Referring to FIG. 10, a lower surface of another arrangement of semiconductor die 52b is depicted in a flip-chip configuration comprising a plurality of solder balls 87 arranged in an array. As depicted, source pads of semiconductor die 52b and solder balls coupled therewith and drain pads of semiconductor die 52b and solder balls coupled therewith are depicted in alternating columns 140, 142, respectively.

[0089] A column 144 comprises both source solder balls (S), kelvin source and drain solder balls (KS, KD), temperature sensing diode solder balls (DP, DN), gate drive amplifier solder ball connections including ground (VSS), input (Gin), and 2.5 Volts (VDD) in one exemplary embodiment.

[0090] In an alternative embodiment, one or more columns of drain 142 or source 140 solder balls can be assigned to Vdd in order to reduce the inductance and resistance of the Vdd connection. This can be accommodated at the external contact level of FIG. 12 by running the metal layers contacting these Vdd columns out the bottom direction in FIG. 12 (in which the source and drain are on the right and left sides), or the Vdd contact might be extended to the right beyond the source contact region.

[0091] Referring to FIG. 11, an alternative package 73c of assembly 70c is depicted for coupling with electrical interconnects 84 comprising solder balls 87. Package 73c is implemented as a vertically laminate package comprising a plurality of conductive layers including source conductive layers 150 and drain conductive layers 152 in an alternating arrangement to couple with solder balls 87 of the flip-chip configuration of semiconductor die 52b shown in FIG. 10. Layer 154 corresponds to the column 144 of miscellaneous solder ball connections described above. Package 73c may also be utilized in conjunction with other die configurations, including the arrangements of semiconductor die 52 described above, and die 52a having intermediate layers 74 illustrated in FIG. 9. Other assembly configurations of dies and packages are possible.

[0092] Still referring again to FIG. 11, a plurality of alternating dielectric layers 153, 155 are provided intermediate appropriate conductive layers 150, 152, 154 as shown. In one convenient exemplary fabrication approach, dielectric layers 153 comprise PC board layers to which the conductive layers 150, 152 are bonded, while dielectric layers 155 comprise B-stage adhesive layers which are used to bond the various PC board layers together using, for example, the same type of lamination processes used to fabricate multi-layer printed circuit boards. In FIG. 11 the metal layers are shown extending a substantial distance 92 above the extent of the circuit board and inter-board adhesive layers in the area where contact to the solder balls is made. Typically this “pullback” region 92 from which the PCB and inter-board adhesive layers are absent can be fabricated by means of an etching or other removal process after the vertical laminate package is fabricated. This form of embodiment of the invention is anticipated to offer potential benefits in reducing stress on the solder balls due to differential thermal expansion between the semiconductor die 52b and the package 73c by allowing the metal layers 150, 152 to bend in the lateral direction in FIG. 11. This beneficial mechanical compliance can be achieved in the opposite direction (that is, in the lateral direction in FIG. 12) by patterning, for example, suitably shaped vertical slots 93 in the source and drain metal planes 150, 152 between the solder ball contact areas, such that the solder ball contacts are made at the top of metal “towers” which have substantial freedom to bend.

[0093] Flip-chip mounting large silicon die directly to copper or thick PCB materials may cause severe reliability problems because of the large differences in CTE between the materials (Si=3 ppm/° C., Cu=16.6 ppm/° C., PCB=19 to 32 ppm/° C.) which fatigues and breaks solder balls on thermal cycling. In a typical PCB process, the metals are backed by a PCB dielectric. In one fabrication method, the structure as shown is originally fabricated with the PCB dielectrics going all of the way to the top. The PCB dielectrics are etched away or otherwise removed to provide flexible metal towers 95.

[0094] Referring to FIG. 12, vertical laminate package 73c is illustrated in a side view coupled with semiconductor die 52b and electrical interconnects 84. A source layer 150, shown in solid outline, is coupled with electrical interconnects 84 comprising source solder balls and extends to the right to provide source terminal 80a. A drain conductive layer 152 is depicted extending in an opposite direction from source conductive layer 150 to provide drain terminal 82a. Both source 150 and drain 152 layers may be patterned with vertical slots 93 or other suitable compliance patterning features between solder balls to achieve lateral compliance, particularly when used in conjunction with the pullback 92 of the PCB and inter-layer dielectrics from the ends of the conductor towers 95 on which solder ball contact is made. Suitable electrically insulative underfill material, not shown in FIG. 12, may be provided intermediate die 52b and package 73c.

[0095] A vertical laminate package 73c provides ultra-low ON resistance (Ron) performance. As shown in FIG. 12, orientation of alternating conductive metal layers 150, 152 in a laminate stack perpendicular to a surface of semiconductor die 52b permits very large reductions in package metal resistance by extending the package structure vertically. Package 73c depicted in FIG. 12 may be utilized by providing electrical interconnects 84 directly upon semiconductor die 52 (e.g., flip chip arrangement) or with the utilization of additive fineline metallization layers 74d, 74e upon semiconductor die 52a as described above in the exemplary configuration of FIG. 9.

[0096] Packaging concepts described herein provide high current conduction while also taking advantage of low Ron capabilities of deep submicron lateral MOSFET devices realized not only at the semiconductor device level but also at the packaged device level. Currents applied to individual power semiconductor switching devices 50 are divided into a large number of parallel paths with increasing metallization or other conductor thicknesses as the number of paths decreases. For example, it has been demonstrated that 250,000 individual MOSFET source and drain electrodes are coupled with 256 solder ball contacts through the utilization of layers of metallization 100 described above upon semiconductor die 52. The packaging coupled with the semiconductor die further reduces the number of contacts from 256 in the given example to a single source terminal contact and a single drain terminal contact comprising high current package leads.

[0097] Referring to FIG. 13, details regarding exemplary transistors 174 utilized to form an exemplary power semiconductor switching device 50 are illustrated. As described above, aspects of the present invention provide power semiconductor switching device 50 comprising a plurality of transistors 174 coupled in parallel to conduct the large currents (1-1000 Amperes) typically experienced in power applications. The number of transistors 174 provided to form a single device 50 is varied depending upon the particular application of power semiconductor switching device 50 and the magnitude of currents to be switched. Six n-channel transistors 174 are depicted in FIG. 13 for discussion purposes.

[0098] Semiconductor die 52 includes transistors 174 fabricated using deep submicron CMOS integrated circuit processes according to exemplary aspects of the present invention. CMOS integrated circuit metallization layers (FIG. 8 and FIG. 9) are provided upon die 52 and are optimally patterned for distributing high currents with low resistance and maximum current handling capability as described previously in exemplary embodiments.

[0099] The present invention provides planar high-current (imax=1 to 1000 Amperes) switching MOSFET devices having very low ON resistance (Ron=10 micro ohms to 1 milliohm typical) and relatively low gate drive power requirements for very high efficiency in low voltage power conversion applications. As described above, the planar device structure of transistors 174 comprising power semiconductor switching device 50 provides structures wherein current flows between closely spaced (e.g., 0.1 to 0.5 microns) source and drain electrodes on the same (top) surface of the semiconductor die 52. Accordingly, aspects of the present invention provide devices 50 comprising high current, low Ron parallel-coupled MOSFETs fabricated upon a relatively small semiconductor die 52 using submicron to deep submicron CMOS integrated circuit foundry processes.

[0100] FIG. 13 depicts a portion of the exemplary power semiconductor switching device 50 comprising plural planar, horizontal geometry high current switching MOSFET devices implemented in a CMOS process. Power semiconductor switching device 50 is fabricated within a monolithic semiconductive substrate 56, such as silicon, comprising die 52.

[0101] Portions of substrate 56 are formed to comprise p-type substrate material 168 or p-wells in which to form n-channel devices 174. In addition, other portions of substrate 56 may be n-type doped to form n wells 170 to enable the formation of p-channel devices 175 if desired. An inter-layer dielectric-filled trench region 172 is typically provided for lateral electrical isolation of n wells 170 from p-type substrate material or p wells 168.

[0102] First metal layer 110 of metallization 100 is depicted in FIG. 13 comprising source electrodes 160 and drain electrodes 162 coupled with respective source diffusion regions 161, 163 which correspond to diffusion regions 101. Gate electrodes 164 are provided intermediate opposing source and drain electrodes 160, 162 and insulated from the semiconductor by a thin gate oxide to form n-channel transistors 174.

[0103] A plurality of source regions 161 and drain regions 163 are formed in p-type substrate 168 for the formation of n-channel devices 174. Regions 161, 163 are doped with an n-type dopant to form n+ source and drain regions in the exemplary embodiment. A polysilicide layer 165 may be provided intermediate electrodes 160, 162 and respective diffusion regions 161, 163 in one embodiment to minimize resistances therebetween. In FIG. 13, the via conductors 173 between the first level metal 110 and the polysilicide layer 165 are shown as part of the source electrodes 160 and drain electrodes 162. Gate electrodes 164 individually comprise polysilicide in one embodiment which are configured to couple with layers of metallization 100. As utilized herein, the term “source” refers to structures including electrically conductive structures proximately coupled with a source of the power transistor and including source contact 160 and/or source region 161 for example and the term “drain” refers to structures including electrically conductive structures proximately coupled with a drain of the power transistor and including drain contact 162 and/or drain region 163 for example.

[0104] Source and drain regions 161, 163 are individually utilized to form a plurality of adjacent transistors 174 in the depicted exemplary embodiment. For example, a given source electrode 160 and source region 161 are utilized to form a transistor 174 with the drain electrode 162 and drain region 163 to the right as well as being utilized in combination with the drain electrode 162 and drain region 163 to the left of the given source electrode 160 to form another transistor device 174. Accordingly, in a power device 50 configured according to this exemplary aspect and having x number of transistors 174 coupled in parallel, x gates 164, x/2 source electrodes 160 and x/2 drain electrodes 162 are utilized.

[0105] As depicted, semiconductive substrate 56 has a surface 57. Source electrode 160, source region 161, drain electrode 162, drain region 163 and gate electrode 164 are formed adjacent to surface 57 in the depicted embodiment according to the horizontal planar configuration of CMOS-implemented transistors 174.

[0106] Source regions 161 may be connected with the p-wells in order to avoid or minimize potential problems with floating p-wells at excessive dV/dt occurrences. Other configurations of transistors 174 are possible.

[0107] Power semiconductor switching devices 50 individually comprise a plurality of planar horizontally configured submicron MOSFET transistors 174 individually including a source electrode 160, drain electrode 162, and gate electrode 164. According to one exemplary embodiment, a single power semiconductor switching device 50 comprises 500,000 or more transistors 174 coupled in parallel to provide a low voltage, high current power device 50. In such an embodiment, source electrodes 160 of transistors 174 are coupled in parallel, drain electrodes 162 are coupled in parallel and gate electrodes 164 are coupled in parallel. Provision of parallel coupled n-channel devices 174 enables power device 50 to conduct currents in excess of one Ampere. An exemplary device 50 comprising 500,000 transistors 174 coupled in parallel on a 4 mm×4 mm silicon die 52 enables conduction of currents up to approximately 200 Amperes.

[0108] The number of transistors 174 implemented within a given device 50 varies depending upon the application or implementation of device 50, as well as the width selected for the individual transistors to be paralleled (taken as 25 microns for the examples cited herein). The current handling capability, die size and Ron values for a device 50 vary corresponding to the numbers of transistors 174 utilized. For example, a very small semiconductor die 52 having an approximate area of 0.16 mm2 provides approximately 5,000 parallel-coupled transistors 174 which conduct currents of approximately 2 Amperes with an Ron of approximately 0.01-0.02 Ohms (inclusive of n-channel MOSFET ON resistance and on-chip metallization resistance, but not including package resistance), while a die of 1.6 mm2 provides approximately 50,000 parallel-coupled transistors 174 enabling conduction of currents of approximately 20 Amperes with an Ron of approximately 0.001-0.002 Ohms, and a die area of 16 mm2 provides approximately 500,000 parallel-coupled transistors 174 which enables conduction of currents of approximate 200 Amperes with an Ron of approximately 0.0001-0.0002 Ohms, and a die area of 80 mm2 provides approximately 2,500,000 parallel-coupled transistors 174 which conduct currents of approximately 1000 Amperes with an Ron of approximately 0.00004-0.00008 Ohms. Further details of FIG. 13 are discussed in the Appendix with reference to FIG. 1B and the associated text thereof.

[0109] FIG. 14 depicts an elevational plan view of a region of an exemplary semiconductor die 50 illustrating n-channel transistors 174 forming power semiconductor switching device 50. The illustrated region includes a plurality of rows 176 individually including a plurality of transistors 174. The number of rows 176 is varied and the number of transistors 174 within a row 176 is varied depending upon the implementation of device 50, the magnitude of currents to be conducted and desired Ron values. In one exemplary implementation of power device 50 having a row 176 height of 25 microns (corresponding to the width of each of the individual transistors), 500,000 transistors 174, 250,000 source regions 161, 250,000 drain regions 163 and 500,000 gates 164 are provided in a 4 mm×4 mm (16 mm2) die size as implemented in a nominal 0.24 micron feature size CMOS process. The Ron and number of transistors in a given die size are typically closely tied to the IC feature size. The number of transistors also depends on the selection of row height.

[0110] FIG. 14 depicts transistors 174 upon surface 57 of substrate 56 (FIG. 13). Source regions 161, drain regions 163 and gates 164 include polysilicide 165 (FIG. 13). A plurality of via conductors 173 are provided upon respective source regions 161 and drain regions 163 and via conductors 177 are provided upon gates 164 to provide vertical connectivity to first metal layer 110 elevationally over substrate 56 as shown in FIG. 8 and FIG. 9, for example.

[0111] Individual rows 176 provide transistors 174 individually having a channel length of approximately 25 microns. In an exemplary nominal 0.24 micron feature size commercial CMOS process using aluminum metallization, individual rows 176 provide W=250 microns of NFET width in a 10 micron horizontal distance. Polysilicide 165 (FIG. 13) comprising source regions 161 and drain regions 163 provides ohmic contacts of 4 Ohms/Sq. Via conductors 173, 177 provide 7.5 Ohms/cut to reduce current path resistance. Polysilicide comprising gate 164 provides an ohmic contact of 7 Ohms/Sq. In the described exemplary configuration, metal layers 110, 111, 112 and 113 (FIG. 8 or FIG. 9) have sheet resistances of 0.08 Ohms/Sq., while the top metal layer 114 has a sheet resistance of 0.04 Ohms/Sq., with a via resistance of 5 Ohms/cut between all metal layers. Other constructions of transistors 174 and connections to transistors 174 are possible. In particular, the Ron and current carrying capacity of the devices could be improved if a CMOS or other IC process using copper, rather than aluminum, metallization is used for fabrication. Further details regarding substantially similar or alternative constructions of FIG. 14 are discussed in the Appendix with reference to FIG. 4A and the associated text thereof.

[0112] Referring to FIG. 15, power semiconductor switching device 50 is illustrated as a power transistor having source terminal contact 80, drain terminal contact 82 and a gate electrode 83. Power semiconductor switching device 50 is coupled with an exemplary gate driver amplifier 180 utilized to drive the gate electrode of power device 50 coupled with a plurality of parallel-coupled gates of transistors 174. Amplifier 180 is one exemplary configuration of amplifiers 60 described above. More specifically, gate driver amplifier 180 may be implemented as auxiliary circuitry 54 upon semiconductor die 52 in one configuration as described above and corresponding to amplifiers 60 of FIG. 4.

[0113] The illustrated exemplary gate driver amplifier 180 includes a first stage 182 and a second stage 184. First driver stage 182 includes a p-channel device 186 wherein Wd1p=2 mm and an n-channel device 188 wherein Wd1n=1 mm. Second driver stage 184 includes a p-channel device 190 wherein Wd2p=100 mm and an n-channel device 192 having Wd2n=50 mm.

[0114] An input node 193 is configured to receive control signals from an appropriate source, such as power converter controller 38, in one embodiment. In the configuration wherein power semiconductor switching device 50 comprises 540,000 n-channel devices an input capacitance at node 193 is approximately 4.5 pF. At a node 194 intermediate first stage 182 and second stage 184, a capacitance of approximately 225 pF is present. Node 195 of second driver stage 184 is coupled with gate terminal 83 of power semiconductor switching device 50 where a capacitance of approximately 20 nF is present.

[0115] Power semiconductor switching device 50 comprising 540,000 transistors 174 coupled in parallel provides Wen=13,500 mm. Power semiconductor switching device 50 conducts currents of 200 Amperes in the depicted embodiment with a 5 mm×5 mm die size and can accommodate currents of 1000 Amperes if the switching device, amplifier and die size are scaled up to a 10 mm×10 mm die size. In the exemplary 0.24 micron CMOS process, VOD is approximately 2.5 Volts and VSS ground in the illustrated arrangement, assuming the source terminal 80 to be near ground potential as used in FIGS. 3 and 4.

[0116] According to certain aspects of the invention, a bypass capacitor 200 is coupled with the source of power semiconductor switching device 50 and VDD. Bypass capacitor 200 is greater than or equal to 20 nF in the depicted exemplary embodiment. Bypass capacitor 200 is configured to provide adequate pulse current to charge a capacitance of the gates of paralleled coupled transistors 174 of power semiconductor switching device 50 responsive to control signals received via input 193.

[0117] In one embodiment of this invention, bypass capacitor 200 is implemented monolithically on a CMOS chip using gate to channel capacitance of a large number of large gatelength (e.g., Lg=10 microns) n-channel MOSFETs in parallel with their common gate electrode connected to Vdd 184 and their source and drain electrodes connected to the output source electrode 80.

[0118] In addition, connecting the source of n-channel device 192 with the source of power semiconductor switching device 50 obviates a need for a separate body diode inasmuch as power semiconductor switching device 50 turns on if the drain 82 thereof becomes substantially more negative than the source 80. Alternative body diode configurations are described below. Further details of the exemplary circuitry of FIG. 15 are described below with reference to FIG. 8 of the Appendix and the associated text of the Appendix.

[0119] Referring to FIG. 16, power semiconductor switching device 50 is depicted coupled with an active diode connected p-channel MOSFET 202. The drain 206 and gate 208 of the p-channel MOSFET 202 are connected as illustrated to provide a body diode circuit turning on when the drain 206 becomes more negative than the source 204 by an amount greater than the threshold voltage Vt of transistor 202. As opposed to a conventional prior art vertical geometry power MOSFET of FIG. 1 and 2 in which the diffusion stored charge, Qd in the body diode 7 can be very large, and a serious limitation to switching speed and efficiency, the stored charge in exemplary devices 50 according to aspects of this invention (e.g., FIG. 16) is very small, principally that stored in the gate capacitance of the switching device 50.

[0120] If the gate 83 of power semiconductor switching device 50 is constrained to go no more negative than the source 80, it inherently acts as a body diode and transistor 202 may be omitted if desired. As a consequence, with the gate driver amplifier configuration of FIG. 15, in which the voltage at the gate terminal 83 of the switching device 50 is constrained to go no more negative than that at its source 80, this n-channel MOSFET active body diode is obtained automatically in the switching device 50. For this exemplary device 50, the stored charge that is removed in switching from a 200 Ampere active body diode current (typically at Vds=−0.75 Volts) to Vds=0 Volts is less than about 15 nanoCouloumbs, which is far less than for conventional prior art vertical geometry power MOSFET devices (FIGS. 1 and 2). Alternatively, device 202 is implemented as an n-channel MOSFET in another embodiment with the gate 208 thereof connected to the source 204 thereof to also serve as an active body diode circuit. Body diode circuit implementations are coupled with the source 80 and drain 82 of the power semiconductor switching device 50 in the depicted embodiment to conduct free wheeling currents which may be present within power converter 10 during switching operations or present during operations in other applications. Further details of FIG. 16 are discussed in the Appendix with reference to FIG. 2B and the associated text thereof. Other circuit configurations to conduct free wheeling currents are possible.

[0121] Aspects of the present invention provide a plurality of planar, horizontally configured MOSFET devices 174 configured to form a power semiconductor switching device 50 having contacts including a high-current source terminal contact 80 and high-current drain terminal contact 82 on a common surface 57 of a semiconductor die 52. Additional aspects enable electrical connectivity of terminal contacts 80, 82 to devices provided upon the common surface 57 of semiconductor die 52 using convenient package configurations. Other aspects of the invention are contemplated and provided, some of which are described above and in the attached Appendix, the contents of which are incorporated herein by reference.

[0122] For comparison purposes, power semiconductor switching devices 50 configured according to exemplary aspects of the present invention including an exemplary 0.24 micron feature size (0.19 micron Leff) CMOS process are discussed below with respect to a conventional vertical power MOSFET (FIG. 1) having equivalent ON resistance Ron values. Power semiconductor switching devices 50 of some aspects of the invention have twenty four times smaller die area than conventional vertical arrangements, approximately thirty times less gate capacitance, 478 times lower gate drive power at a given frequency (Pgate/fclock) and the exemplary semiconductor die configurations described herein may be fabricated by a standard CMOS integrated circuit foundry if desired as opposed to processes to form vertical conventional configurations.

[0123] FIG. 17-FIG. 19 depict respective graphical representations 240, 250, 260 of electrical performance characteristics of an exemplary power semiconductor switching device 50 which embodies aspects of the present invention. The graphed power device 50 comprises a 200 Ampere power device 50 having 514,000 n-channel MOSFETs 174 providing W=12,850,000 microns and Leff=0.19 microns.

[0124] FIG. 17 depicts drain currents of the exemplary power device 50 for values of VGS=0.5−2.5 Volts in 0.5 Volt increments over its nominal 0 to 2.5 Volt drain voltage range and over an Id=0 to 8000 Ampere range high enough to include its Idss=7700 Ampere saturated drain current at Vgs=+2.5 Volt value. Note that sustained operation at high values of drain currents (e.g., above 200 Amperes) may not be possible because of metal migration reliability issues, and operation at combinations of high drain voltages and drain currents should be kept of short duration because of thermal power dissipation and energy absorption limitations.

[0125] FIG. 18 depicts drain currents of the exemplary power device 50 for values of VGS=0.45-0.7 Volts in 0.05 Volt increments over its nominal 0 to 2.5 Volt drain voltage range and over the Id=0 to 200 Ampere range within which sustained operation is specified (subject to power dissipation and energy absorption limitations).

[0126] FIG. 19 depicts drain currents for a VGS value of 2.5 Volts over the Id=0 to 200 Ampere range within which sustained operation is specified and over the 0 to 0.05 Volt drain voltage range within which sustained operation is normally seen for a device of this size when the device is ON (Vgs=+2.5 Volts) in the exemplary power conversion applications of the type illustrated in FIGS. 3 and 4.

[0127] Reference 262 of FIG. 19 depicts, at any given drain current within transistors 174 of an exemplary power device 50, the voltage drop, Vds, measured from the transistor drain contact 163 to source contact 161 in FIG. 13 assuming approximately equal sharing of total current Id between all transistors 174. The slope of this line is the Ron of the transistor devices 174 themselves, exclusive of on-chip or package metal resistance.

[0128] Reference 264 depicts, at any given drain current, the voltage drop, Vds, measured from the chip drain pads 118 to source pads 116 in FIG. 8, assuming approximately equal sharing of total current Id between all source 116 and drain 117 pads. The slope of this line is the Ron of the transistor devices 174 themselves plus that of the on-chip metallization 100 for the case of a 4 mm×4 mm die having a total of 256 solder balls, exclusive of package metal resistance.

[0129] Reference 266 depicts at any given drain current, the voltage drop, Vds, measured from the package drain contact 82 to package source contact 80 in FIGS. 5 and 6, assuming uniform distribution of current across the width of these package contacts 80, 82, for the case of a 4 mm×4 mm die having a total of 256 solder balls and the package metallization thicknesses discussed in conjunction with FIGS. 5 and 6, and in Appendix A. The slope of this line is the total Ron of the packaged transistor inclusive of the transistor devices 174 themselves plus that of the on-chip metallization 100 and the package metal resistance.

[0130] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

APPENDIX A

SUMMARY OF THE INVENTION

[0131] The use of diodes for output current rectification in low output voltage switching power converters or power supplies is precluded by the severe loss in efficiency due to the forward voltage drop of diodes becoming comparable to the desired output voltage, Vout,of the converter. The use of MOSFETs or other similar high-current switching devices in a synchronous rectifier approach can overcome this efficiency problem if the “on” resistance, Ron, of the current switching MOSFETs is sufficiently low to make the IoutRon voltage drop of across the switches much lower than Vout. This can be achieved with conventional MOS power FETs by making the FET periphery (total channel width, W) very large, either by making one very large device, or by connecting many smaller devices in parallel. In either approach, to achieve very low Ron values, the device cost becomes quite large due to the large size of a single die, or the large number of paralleled devices. Also, the total gate capacitance of all of these devices becomes very large, which limits the attainable switching speed and causes significant losses in converter efficiency due to the large ac gate drive power requirements.

[0132] Aspects of the present invention take advantage of the fact that in a switching converter application, the breakdown voltage, Vb, required for the synchronous rectifier switching devices is, for an output voltage of Vout, only about Vb=2Vout. For example, for an output voltage of Vout=1.2V, a breakdown voltage of about Vb=2Vout=2.4V is adequate for the synchronous rectifier MOSFET switches. In aspects of this invention, this low breakdown voltage requirement is exploited to enable implementation of the synchronous rectifier switching MOSFETs with an inexpensive commercial deep-submicron CMOS integrated circuit foundry process (instead of the special higher voltage process normally used for fabricating power MOSFET devices). For a given Ron, compared to standard MOS power FET processes, the use of a very short channel length (e.g., Leff=0.19 μm)/very small feature size (e.g., 2λ=0.24 μm) commercial IC process for fabricating the current switches dramatically reduces the size and cost of the devices, and also greatly reduces the gate capacitance and increases switching speeds for higher efficiency and smaller converter size.

[0133] The dramatic size/cost reduction comes through the combined effect of a reduction in the MOSFET periphery, W, required to achieve a given value of Ron (because of the very small Leff), with the fact that the very small feature size allows packing a given MOSFET periphery into a much smaller chip area. For example, at the silicon device level, an extremely low “on” resistance of less than Ron=75 μΩ can be achieved for a 200 amp switching MOSFET with a total Leff=0.19 μm FET periphery of less than W=13.5 meters, and with a 2λ=0.24 μm feature size, this W=13.5 meter MOSFET can be packed into a chip only 4 mm×4 mm in dimensions. At an estimated foundry CMOS foundry wafer cost of $1500 per 8″ (200 mm) wafer, the unpackaged die cost for such a 200 amp switching MOSFET chip should be less than $1.00. This deep-submicron approach gives not only a much smaller solution to achieving an extremely low Ron 200 amp current switching MOSFET, but promises to be 10× to 100× cheaper than implementations using standard power MOSFET processes. In addition, because of the reduced FET periphery and very short (Lg=0.24 μm drawn) gate length, the gate capacitance is far lower, and the switching speed much higher than in the power MOSFET implementation, and the ac gate drive power at a given switching frequency can be reduced by nearly a factor of 500 over conventional vertical geometry power MOSFETs.

[0134] Also important to some aspects of this invention is the solution of the A problem of getting such large (e.g., 200 amp) currents into and out of the small (e.g., 4 mm×4 mm) FET chip without encountering metal migration reliability problems or unduly compromising Ron from the on-chip metal resistance or package resistance. Conventional power MOSFETs take the source and drain currents out of opposite faces of the die (e.g., all of the area devoted to source contacts, plus the gate leads, are on the top surface of the die, while the drain contact is the entire back surface of the die. Having the high-current source and drain contacts on opposing surfaces of the die makes the die packaging/interconnect quite easy. A disadvantage of using a CMOS integrated circuit process instead of a power MOSFET process is the unavailability of this backside drain contact configuration. The MOSFET geometries in commercial CMOS IC processes are purely lateral; that is a source-gate-drain electrode structure on the top surface of the semiconductor die. Hence, in order to implement aspects of this invention and use a commercial deep-submicron CMOS process to make the low Ron current switching MOSFETs, we have to be able to get both the high current source and drain contacts (plus one or more gate leads) off of the same (top) surface of the die. The key to the solution of this high-current chip packaging/interconnect interface problem is to cover at least substantially the entire area of the die with a fine pitch area array of solder bump contacts which flip-chip mate with a matching array on a very low resistance multi-layer metal package. It is desirable that the pitch of these solder bump contacts be as low as possible to minimize the metal resistance. While a standard commercial practice area array bump pitch of 250 μm is adequate to give a total (i.e., silicon FET+on-chip metal+solder bump+package metal) resistance of the order of 285μΩ, with a smaller, 100 μm bump pitch (which is also commercially available), the total Ron can be reduced to less than 180μΩ for the MOSFET chip example cited above. This very low resistance is a result of the sharing of the source and drain current by a large number of solder bump contacts (e.g., 126 bumps each for the 250 μm pitch and about 800 bumps each for the 100 μm pitch, which accounts for its better Ron performance).

[0135] In summary and in accordance with exemplary aspects of the invention, the use of a commercial deep-submicron CMOS integrated circuit process in conjunction with an area array solder bump flip-chip packaging approach allows the achievement of high-current (e.g. 200 amp), very low on resistance low voltage MOSFETs having much lower cost and much lower gate capacitance, not to mention much smaller size, than devices implemented using conventional power MOSFET processes.

BACKGROUND OF THE INVENTION

[0136] A key focus of modern digital electronics is to achieve extremely high computational densities; that is, to cram as much computational throughput as possible into a limited space. The relationship between something as seemingly tenuous or intangible as computational power and a simple concrete physical quantity like dc power input or waste heat generated may not be obvious. In fact, computational throughput (“power”) is, as a matter of physics, tied to the conversion of dc input supply power to heat. Moreover, in the most efficient forms of logic circuitry, the level power consumption/heat generation is essentially proportional to the computational throughput, albeit the exact value of the constant of proportionality is dependent on details of the integrated circuit (IC) technology used to implement the computer. Specifically, it can be shown that for CMOS logic (in which the dynamic power dissipation dominates), a chip with Ng gates, each driving an average load capacitance, Cgl, operating at a supply voltage, Vdd, and at a clock frequency, Fc, with a fraction, fd, of those gate switching on each clock cycle, the chip power, Pd, will be given by

Pd=½fdNgCglVdd2 Fc  Eq. 1

[0137] Since a reasonable measure of computational activity is the number of such logic gates that have switched, the measure of computational throughput (rate) is simply the number of such logic gates switching per unit time, fdNgFc, or

Computing Rate ∝fdNgFc=Pd/[½CglVdd2]∝Pd  Eq. 2

[0138] which shows the (technology dependent) proportionality between computational throughput and the power consumed (dissipated). What this means is that the quest for high computational density forces designers to cope with both high power supply densities, as well as the ability to handle high reject heat densities.

[0139] Advances in integrated circuit technologies, principally through the reduction in lithographic feature sizes and FET gate lengths into the deep submicron region, have made it possible to put millions of logic gates on a single monolithic IC chip, as well as to increase clock rates, Fc, into the 500 MHz to 1 GHz region. This means, from Eq. 2, that since both ng and Fc have been increased, remarkably high computational throughputs can be achieved even on a single chip microprocessor. While feature size reductions also serve to reduce CMOS FET gate capacitances (Cgs and Cgd), much of the gate loading capacitance, Cgl in Eqs. 1 and 2, is due to interconnect wire capacitance, which is principally a function of wire length, and hence does not scale strongly with feature size. This means that if the logic power supply voltage were held constant, the chip dissipations would become astronomical (e.g., many kilowatts) for these very dense, high throughput chips. This problem has been recognized by the semiconductor industry, and as a consequence the power supply voltages have been gradually reduced over the last decade from their original Vdd=5.0 V level down to Vdd=1.2 V for the latest 2λ=0.24 μm feature size, Leff=0.19 μm gatelength CMOS logic.

[0140] While this reduction on Vdd has helped keep chip power dissipations to a manageable level (typically under 100 W to 200 W per chip), which helps the thermal management problem, in fact it has in some ways made the power supply/distribution problem even more difficult. The problem is that while the chip power requirements have been maintained at tolerable levels, the power supply current requirements have increased sharply, while at the same time the tolerance for IR voltage drops in the power distribution conductors has become more severe. For example, consider a logic power (in one or more chips) requirement of Pd=240 W. In the “old days” of Vdd=5 V logic, from Pd=VddIs, the required supply current would be Is=240/5=48 amps, and for a 10% dc noise margin allowable Vndc=IsRs=0.5 V drop, the allowable wiring resistance between the power supply and the logic is Rs=0.5/48=10.4 mΩ. With the reduced Vdd=1.2 V logic, the required supply current would be Is=240/1.2=200 amps, and for a 10% dc noise margin allowable Vndc=IsRs=120 mV drop, the allowable power distribution resistance from supply to logic is only Rs=0.12/200=600μΩ. It is probably obvious that it is very difficult to achieve such low power distribution resistances. While it is correct that the use of an on-board regulator near the logic chips could make it much easier to meet the dc noise margin requirements of the logic, note that at Is=200 amps, even a Rs=1.0 mΩ wiring resistance (including the regulator resistance) between the power supply and the logic chips will reduce the power efficiency by over 14%, so sub-millivolt resistances are indeed required. Conventional circuit board connectors, etc., are not capable of handling 200 amp currents with sub-millivolt resistances, so another approach is needed.

[0141] The most attractive approach to solving this problem is to distribute the power to the boards at a high voltage (e.g., Vin=48 volts), using very efficient on-board power converters to convert this to the Vdd=1.2 volt logic supply level. In order to insure that the on-board power conversion does not unacceptably compromise the overall density of the electronics, it is desirable to make the on-board power converter as small as possible. In a switching converter, the stored energy requirements in the magnetics (e.g., transformers and inductors) and in bypass or filter capacitors can be reduced by increasing the switching frequency, fs, of the converter. This is difficult, however, because of the limited switching speeds of most semiconductor devices capable of handling large currents. Addressing this deficiency is one focus of aspects of this invention; that is to provide low cost MOSFET switches capable of handling high currents at high switching speeds.

[0142] While the use of on-board power conversion to efficiently supply low voltage logic requirements in high-performance systems is extremely attractive, there is an inherent difficulty with achieving high efficiency, very small low voltage power converters. The ordinary method of building a switching converter involves a transformer to convert down to low voltage ac, with diodes to rectify this to dc. If the forward voltage drop of these rectifier diodes is Vf and the output voltage is Vout, then the voltage loss in the diodes alone will limit the attainable rectifier efficiency, ηr, to a value less than

ηr≦Vout/(Vf+Vout)  Eq. 3

[0143] Typical Schottky diode forward voltage drops are of the order of Vf=0.55 V or more. In the “old days” of 5 volt supplies, this diode efficiency limit, about ηr=90%, was quite acceptable. With the new low supply voltages, this is no longer the case, as Eq. 3, with Vf=0.55 V, gives a limiting efficiency of about ηr=69% at Vout=1.2 volts, or about ηr=62% at Vout=9 volts. These are unacceptably low values of conversion efficiency.

[0144] The solution to this problem is to employ MOSFET current switches in place of the diodes (this approach is called synchronous rectification). If the MOSFET “on” resistance, Ron, is sufficiently low, this rectification efficiency loss may be kept very low. Unfortunately, using commercial devices fabricated with the standard vertical “power MOSFET” device structure, to get a low enough Ron value, it is often necessary to parallel large numbers of power MOSFET devices in each of the two current switching positions in the circuit. Also, the enormous gate capacitance of all of these power MOSFETs makes gate drive very difficult and causes significant efficiency loss due to ½ CgsΔVg2 Fc gate drive power. This, plus the limited switching speeds of the standard power MOSFET devices, effectively limits the usable switching frequency of the converters. Since the size of the magnetics (and capacitors) goes inversely with the frequency, this makes it very difficult to miniaturize the converters for on-board use (of course, having large numbers of power MOSFETs gives a size problem itself).

DESCRIPTION OF EXEMPLARY ASPECTS OF THE INVENTION

[0145] Aspects of the invention achieve extremely low Ron values and extremely low gate capacitances/high switching speeds in a MOSFET current switching device, including a packaging approach enabling it to be used in circuits. Some concepts of the invention use a completely different device structure from the vertical geometry of power MOSFETs; in fact, to make current switching MOSFETs in a horizontal (planar) geometry using the same 0.25 μm to 0.18 μm CMOS IC processes that are used to fabricate the high-speed logic chips themselves. While the transistors in these deep-submicron short-channel CMOS processes have only about 2.5-3 volt breakdown voltages, for a synchronous rectifier having Vout=1.2 volt, a Vbr=2.4 volt breakdown voltage is adequate for the transistors. With this approach, in a chip only 4 mm×4 mm in size, it is possible to switch currents of 200 amperes and to achieve a value of Ron superior to that of the parallel combination of dozens of power MOSFETs, and at a very small fraction of the gate capacitance. This makes it possible to reduce the ac gate drive power required to switch to a given Ron value at a given switching frequency by nearly a factor of 500 over conventional vertical power MOSFETs.

[0146] Other aspects of the invention provide a packaging approach capable of getting 200 amperes into and out of such a small chip without substantially degrading the Ron value. Whereas the vertical geometry of a conventional power MOSFET has the source lead on the top surface of the die and the drain lead on the bottom, in the horizontal or planar MOSFET structure, the source and drain leads (as well as the gate connection) are on the top surface of the device. On-chip metallization layers on semiconductor die generally have substantial sheet resistances (e.g., 40-80 mΩ/square) and limited current carrying capacity. This makes combining the distributed MOSFET currents from the myriad of elemental MOSFET devices spread over the area of the chip into single source and drain MOSFET chip contacts on the top surface of the die without unacceptably degrading both Ron and the current switching capacity of the chip. In aspects of this invention, a solution to this packaging/interconnection problem for current switching MOSFETs fabricated in the horizontal or planar structure is to utilize an area array of a large number (many hundreds to thousands) of chip source and drain contact pads (plus gate pads) covering the top surface of the die. With the very large source and drain currents divided into a large number of parallel paths, the aggregate current carrying capacity can be very large and the metal contribution to the chip on resistance can be small. The area pad array may be flip-chip mated to a mirror-image area pad array in a very low resistance package. A multi-layer package approach utilizing thick copper interconnect layers has been designed to meet the requirements of contacting such an area array planar current-switching MOSFET chip with capability for handling 200 ampere currents with package contribution to total on resistance of less than 100μΩ.

[0147] The achievement of an inexpensive, ultra-low on resistance planar current switching MOSFET is anticipated to have a wide range of applications in addition to efficient low-voltage on-board power conversion. Very low Ron MOSFETs could have application in a wide variety of low-voltage high-current applications, ranging from linear applications such as high-current regulators and drivers to switching applications such as efficient high-density power supplies and converters, including solar cell power conversion, and switch-mode drivers for motors and actuators.

[0148] Comparison of Device Structure of Aspects of the Invention to Conventional Power MOSFET

[0149] The dramatic difference between the horizontal or planar geometry current switching MOSFET structure of aspects of this invention and the vertical geometry of a conventional power MOSFET is illustrated in FIG. 1a. FIG. 1a shows the device structure of a conventional power MOSFET. In an N-channel device of this structure, electrons flow from the n+ diffused source regions horizontally across the p body region (which is electrically shorted to the source), through a surface channel. The magnitude of this electron current is under control of the insulated gate. Past the p body region, the path of the electrons turns downward, vertically crossing the n− epitaxial drift region and going into the n+ substrate drain region, the contact for which is on the bottom side of the power MOSFET die. From a MOSFET current control standpoint, the FET channel length, L in FIG. 1a, is determined by the difference in the lateral extent of the p body diffusion and the n+ source diffusion, with values of the order of L=1 μm typical for power MOSFETs. It is important to note that the actual on resistance, Ron, of the standard power MOSFET device is substantially higher than the channel resistance (specifically, the channel resistance plus twice the source resistance, as for a symmetrical planar MOSFET), due to the electron current path passing vertically through the n− drift layer and the n+ substrate thickness to reach the drain contact.

[0150] Comparison of Die Area Required for Deep-Submicron Planar Current Switching MOSFET to Achieve Given Value of Ron to Conventional Power MOSFET

[0151] The principal advantage of this conventional power MOSFET device structure, in addition to its ability to handle comparatively large drain voltages, is its convenient contact arrangement. The high-current drain contact covers the entire bottom of the die, while the high-current source contact covers most of the top of the die, sharing that surface with a smaller gate contact. This convenient die contact arrangement makes it easy to package the chip in a simple high current package. The principal disadvantage of the conventional power MOSFET structure is that even though the structure of source islands with channel borders shown in FIG. 1a is packed into a dense 2-dimensional array covering the die surface, even with an aggressive 106 islands/cm2 (10,000/mm2) array packing density, the potential amount of MOSFET periphery (width, W, of the surface channel per unit area, assuming W=20 μm/island), is only about W/Achip=200 mm/mm2 (reduced by ˜10% for gate contact area). As a comparison, the planar horizontal geometry current switching MOSFET structure according to aspects of this invention gives W/Achip=926 mm/mm2 in a nominal 2λ=0.24 μm feature size CMOS process (or about W/Achip=850 mm/mm2 including gate routing area), 4.63 times higher. Since for a given channel sheet conductance, the channel resistance is proportional to L/W, the other critical dimension for the power MOSFET is the channel length, L. As noted in FIG. 1a, L=1.0 μm is typical for the channel length of a conventional power MOSFET. In comparison, the effective channel length in a 2λ=0.24 μm feature size CMOS process is typically Leff=0.19 μm or less. Hence for the same MOSFET periphery, the deep-submicron short-channel planar MOSFET devices used in aspects of this invention offer nominally 5.26 times lower channel resistance than a conventional power MOSFET. When this is combined with the fact that the periphery available in a given chip area is also 4.63 times higher, for a given chip size, the 2λ=0.24 μm feature size CMOS process planar current switching MOSFETs of aspects of this invention will have a channel resistance over 24 times less than that of a conventional power MOSFET.

[0152] The structure of the horizontal or planar geometry short channel current switching MOSFET is illustrated in Figure ib. The basic device structure consists of a series of parallel n+ stripes with poly silicide contacts, which represent the alternating source and drain electrodes, separated by poly silicide gate electrodes insulated from the silicon surface by a very thin (e.g., tox=5.8 nanometers) insulating layer which allows channel conduction to be controlled fully with very small gate voltage changes (ΔVgs˜2.5V). The electron path is essentially horizontal through the surface channel from the n+ source to the n+ drain electrodes. Typical dimensions in a 2λ=0.24 μm feature size CMOS process are a nominal gate length of 2λ=0.24 μm (Leff=0.19 mm effective channel length), with source and drain contact widths of 7λ=0.84 μm, for a total MOSFET pitch of 9λ=1.08 μm (the reciprocal of which gives the W/Achip32 926 mm/mm2 periphery to area ratio cited above). In fact, it is possible to fabricate substantially higher density MOSFETs in a such a λ=0.12 μm CMOS process, with as low as ˜6λ=0.72 μm pitch, but in aspects of this invention it is desired to keep the total device resistance, including contacts and metal interconnects, as small as possible. Because the sheet resistance of the poly silicide source and drain contacts is relatively high (˜4 Ω/square), it is important to minimize the distance the current passes laterally through the poly silicide contact before it reaches metal. As shown in FIG. 1b, a 7λ=0.84 μm source/drain (S/D) stripe width allows for a continuous chain of poly silicide to M1 (first level interconnect metal) via contacts to be placed down the center of these S/D stripes, making the poly silicide degradation of Ron negligible.

[0153] Comparison of Gate Drive Power Required for Planar Current Switching MOSFET to Achieve Given Value of Ron to that of Conventional Power MOSFET

[0154] To reiterate, the enormous (24× nominal) advantage in required silicon die area to achieve a given on resistance of the planar or horizontal geometry current switching MOSFET structure of aspects of this invention as compared to a conventional vertical power MOSFET structure comes about through the combination of the 4.63× greater FET periphery, W, that can be packed into a given area (due to the smaller feature size), and the 5.26× lower channel resistance for a given periphery (due to the shorter Leff). This greatly reduced die size offers both a greatly reduced die cost and the opportunity for miniaturizing power conversion products. An additional benefit of this approach is the enormous reduction in gate drive power it affords. Ignoring parasitic contributions to gate capacitance, the charge, Qg, furnished to the gate electrode will nominally equal the charge induced in the surface channel of the MOSFET. For an n-channel MOSFET with channel length, L, having a channel electron mobility of μe, the channel resistance, Rch, at low drain voltages will be given as

R ch =L 2 /(μeQg) (for very low Vds)  Eq. 4

[0155] Comparing the L=1.0 μm channel length of conventional vertical power MOSFETs with the Leff=0.19 μm channel length of the planar devices of aspects of this invention means that, for the same ate, the gate charge to reach a given Rch value will be 27.7 times smaller for the new planar current switching MOSFETs. Further, with a gate voltage swing, ΔVgs, the ac gate drive power, Pgd, required to furnish this gate charge (i.e., to charge and discharge the gate capacitance, Cgs+Cgd) at a switching frequency, Fc, will be given by

P gd =½(Cgs+Cgd)ΔVgs2Fc=½QgΔVgsFc  Eq. 5

[0156] The magnitude of the gate voltage swing, ΔVgs, required to transfer the gate charge, Qg,=(Cgs+Cgd)ΔVgs is determined by the gate oxide thickness, tox. The gate capacitance of a MOSFET with channel length, L, and periphery, W, is given by

C gs +C gd =εoεrL W/tox  Eq. 6

[0157] where ε0=8.85×10−14 F/cm and εr=3.9 for an SiO2 gate dielectric. From Eqs. 4-6, the channel resistance of the MOSFET will be given by

R ch =L 2 /(μeQg)=L tox/(μeε0εrWΔVgs)  Eq. 7

[0158] This means that the gate voltage above threshold, ΔVgs, required to reduce the channel resistance to a given Rch value, as given by

ΔVgs=L tox/(μeε0εrWRch)  Eq. 8

[0159] is proportional to the oxide thickness, tox. Substituting Eq. 8 into Eq. 5 shows that the amount of ac gate drive power, Pgd, required to switch the MOSFET to a channel resistance, Rch, will be given by

P gd =½FcL3tox/(μe2Rch2ε0εrW)  Eq. 9

[0160] This is an important result which indicates that a given switching frequency, Fc, for MOSFETs with the same W/L ratio and channel mobility, in addition to the factor of L2 that comes from the required gate charge (Eq. 5), the gate drive power expression has an additional factor of tox in it. Hence, if we compare the planar geometry current switching MOSFET of aspects of this invention with L=Leff=0.19 μm and tox=5.8 nm with a typical vertical geometry power MOSFET having L=1.0 μm and tox=100 nm, we see that in addition to the L2 advantage of 27.7×, we have a tox advantage of 17.24×, which means that the ac gate drive power is reduced by an factor of 478× by going from a conventional vertical power MOSFET to the deep-submicron planar MOSFET structure of aspects of this invention. This amazing (nearly 500×) reduction in gate drive power lets this new planar short channel current switching MOSFET be operated at much higher switching rates without seriously compromising power efficiency, which in turn allows for greatly reducing the size of switching power converters, etc., because of the reduced sizes of the capacitors and magnetic elements.

[0161] It should be noted that while Eq. 5 is exact, due to higher vertical electric fields at the gate oxide interface, the channel mobilities, μe3, in deep-submicron MOSFETs will be somewhat smaller than those for power MOSFETs. On the other hand, while the total MOSFET device “on” resistance, Ron(f), of the planar geometry MOSFETs of aspects of this invention (FIG. 1b) are given from the channel resistance, Rch, and the source and drain contact resistances, Rs and Rd, (normally Rs≅Rd due to symmetry) by

R on (f)=Rch+Rs+Rd≅Rch+2RS(for planar MOSFETs)  Eq. 10

[0162] for the unsymmetrical vertical geometry power MOSFET structure of FIG. 1a, there is a substantial additional drain resistance component due to the n− drift layer in FIG. 1a that makes Ron(f) substantially greater than Rch+2Rs. Hence a substantially lower Rch value must be achieved in the vertical power MOSFET in order to achieve the same total device resistance, Ron(f). Additionally, while Eq. 6 is a good approximation for the gate capacitance in the planar MOSFET structure, the large gate area over the n− drain region (see FIG. 1a) makes the actual gate capacitance at low Vds for the conventional vertical power MOSFET structure much larger than indicated by Eq. 6. Hence the nearly 500× gate drive power advantage of the planar geometry short channel MOSFETs of aspects of this invention over conventional vertical power MOSFETs should at least be reasonably accurate, and probably understates the advantage.

[0163] Capability of Some Embodiments of Invention to Realize Very High-Speed Ultra-Low Qd Body Diode

[0164] The capability of a CMOS integrated circuit fabrication process to make, in addition to the n-channel MOSFETs discussed above, isolated p-channel MOSFETs (as shown in FIG. 1b), can also be exploited to advantage in designing high current switching planar MOSFETs as well. FIG. 2a shows the equivalent circuit of a conventional vertical power MOSFET. Note that, in parallel to the n-channel MOSFET device, there is a robust p-n junction body diode which is capable of passing high levels of current if the drain is made more negative than the source by Vfp-n=1.0V or so. While in some switching circuit applications where the synchronous rectifier switch timing is not precisely matched to the secondary current timing, the “freewheeling” currents can be handled by the p-n body diode. Unfortunately, the relatively high forward voltage drop of the body diode will degrade the power efficiency of low voltage converters substantially if the duration of the freewheeling currents is a significant fraction of the total switching cycle. In addition to the high p-n body diode forward voltage drop, they also have serious charge storage problems (large Qd values) that limit usable switching frequencies. In the short-channel CMOS-implemented planar current switching MOSFET device of aspects of this invention, it is possible to use the p-channel device to implement a relatively low forward voltage drop “diode” having virtually no charge storage (near-zero Qd). The optional circuit for adding this “body diode” capability to an n-channel device is illustrate in the equivalent circuit of FIG. 2b. This “body diode” function is emulated by an active diode-connected p-channel MOSFET (i.e., the gate is connected to the drain). When the drain electrode becomes more negative than the source by a voltage equal to the gate threshold voltage, Vtp, the p-channel device will begin strong conduction. Since a typical value for this gate threshold voltage is Vtp32 −0.28V, the Vfpch forward conduction voltage drop can be much lower than for a p-n junction body diode. When the drain terminal is more positive than the source, as when the n-channel device is conducting normally, the p-channel device conduction is cut off. There is negligible charge storage associated with the transient transition of this diode-connected p-channel MOSFET “body diode” from strong “forward” conduction to “reverse bias” cutoff (principally the small Cgs+Cgd of the p-channel MOSFET plus some n-well to p-substrate capacitance).

[0165] As noted in FIG. 2b, this “body diode” function can equally well be implemented with an n-channel MOSFET whose gate is connected to its source. When the drain electrode becomes more negative than the source by a voltage equal to the gate threshold voltage, Vtn, the n-channel device will begin strong conduction. This is because when the drain of the symmetrical n-channel MOSFET is taken more negative than the source, the source behaves like the drain and visa versa, so the gate is now connected to the (effective) drain, which is the usual configuration for connecting a MOSFET as an active diode. Note that this also means that if we constrain the gate voltage of the “OFF” large n-channel current switching MOSFET to go no more negative than its source [(Vgs)off=0], then this n-channel current switching MOSFET will act, by itself, as a “body diode” with no additional structures necessary.

[0166] Interconnect/Packaging Approach for Ultra-Low Resistance Connection of Deep-Submicron Planar Current Switching MOSFET Die to Circuits

[0167] While the electrical characteristics of the planar geometry deep-submicron current switching MOSFET structure of aspects of this invention represent an enormous improvement over conventional power MOSFET devices in terms of much smaller die sizes, higher switching speeds and remarkably lower gate drive requirements to achieve a given value of on resistance, Ron, it requires a carefully designed interconnect and packaging approach to realize the die-level performance in actual circuit application. The basic approach to achieving this is illustrated in FIG. 3, which shows a cross-sectional view of the planar (horizontal) geometry MOSFET structure with its on-chip interconnects, solder ball array die to package mating, and high-current low-resistance package. Note that in order to maintain visibility of the on-chip interconnect structure, the vertical dimensions of the thicker elements such as silicon die thickness, die to package (and solder ball) thickness, and thickness of package copper layers have been reduced in FIG. 3.

[0168] The basic interconnect/packaging approach is to make use of an area array of a large number of source (S) and drain (D) pads, in addition to a few gate (G) pads, covering the full area of the planar geometry current switching MOSFET die. In a preferred embodiment of this invention, illustrated in FIG. 3, solder balls are formed on each of these pads for flip-chip mating to the mirror-image pad array on the high-current package. As the density of the pad array is increased, or pitch between the solder balls decreased, the height of the solder balls is generally proportionally decreased. Hence as the center-to-center pitch, Psb, of the solder balls is reduced, the number of balls, Nsb, on a chip of area, Achip,

N sb =A chip /P sb 2   Eq. 11

[0169] increases as 1/Psb2, while the resistance per ball, Rpsb, increases as 1/Psb (since the ball height and diameter go as Psb, the height to area ratio goes as Psb/Psb2=1/Psb), so the combined solder ball resistance varies as

R sb =4Rpsb/Nsb∝1/Psb  Eq. 12

[0170] (The factor of 4 in Eq. 12 comes from assuming that if there are Nsb total solder balls on the die, approximately 50% will be used for source contacts and the other 50% for drain contacts, accounting for a factor of 2, while the Ron will be degraded as the sum of the source and drain contributions, accounting for the other factor of 2.) What Eq. 12 illustrates is that the total pad contact resistance can be reduced by making the solder ball pitch as small as possible (the ball array density as large as possible). The pitch effect is even stronger in the reduction of the metal spreading resistance, which tends to fall nearly as 1/Nsb or 1/Psb2. Hence the use of a high-density array of as many solder bumps as possible covering the surface of the die reduces both the solder bump and the metallization (on-chip and package) contributions to the “on” resistance of the packaged planar current switching MOSFET devices. While typical commercial flip-chip solder bump array pitches of Psb=250 μm are adequate for useful performance, the total metallization plus ball resistance can be several times the intrinsic MOSFET device resistance (Eq. 10) (or somewhat less if a copper interconnect metallization technology is used on the chip). By using the highest commercially available solder bump array density, Psb=100 μm, the total (chip plus package) metallization plus solder ball resistance may be reduced by about a factor of three, to make it comparable with the intrinsic MOSFET device resistance (e.g. ˜75μΩ for a 4 mm×4 mm die with a typical aluminum metallization technology).

[0171] On-Chip Interconnects

[0172] In the cross-section drawing of FIG. 3, there are 5 levels of on-chip metallization illustrated, typical for a current 2λ=0.24 μm feature size commercial CMOS IC foundry process. In the cross section drawing of FIG. 3, and in the associated mask layer sequence layout drawings in FIGS. 4A-4B and 5A -5B, the use of the various chip metallization layers is shown. The chip layout actually begins with the shallow trench isolation of the p-well in which the n-channel MOSFETs are defined. While the shallow trench isolation is not illustrated in FIGS. 4A-4B, it would occupy the 3 μm space between the 25 μm high rows of MOSFET channels, somewhat wider than the M1 and M2 gate (G) busses. The upper left layout (FIG. 4A) shows the 7λ=0.84 μm wide by 25 μm long poly silicide source/drain (S/D) stripes, plus the row of 2λ=0.24 μm square via cuts which connect them to the M1 stripes above them. These M1 stripes, plus their vias up to M2 are shown at the upper right (FIG. 4B). The structure up through M1 is also illustrated in the cross sections of FIGS. 1b and 3. As seen at the lower left (FIG. 4C), M2 is dedicated mainly to horizontal S and D busses, plus the smaller horizontal gate bus (which is in parallel to its counterpart on M1). M3, as seen at the lower right (FIG. 4D) (and reproduced at the upper left FIG. 5A) is a dedicated S (source) plane, with a substantial number of drain (D) feedthrus (and a much smaller number of gate (G) feedthrus) penetrating it. Similarly, as seen at the upper right in FIG. 5B, M4 is a dedicated D plane, with S and G feedthru patches to reach up to the S and D contact “checkerboard” (and gate contact “grid” in between) that makes up M5. The lower left drawing in FIG. 5C shows a portion a source and a drain contact pad and the vertical M5 gate “grid” stripe between them (these tie all of the horizontal M1/M2 G busses together into a single gate connection, to which are assigned four M5 gate pads). The total chip layout at the lower right illustrates a 4 mm×4 mm chip carrying 256 solder ball pads on a Psb=250 μm pitch. As illustrated in the cross-sectional drawing of FIG. 3, the actual solder ball base is a 125 μm diameter circle, centered on each of the square M5 contact pads, that is defined by a hole in the oxide protection coating (“scratch mask”).

[0173] Package Interconnects

[0174] Because of the concentration of current, and requirement for carrying the current laterally over substantial (many mm) distances, the metallization thicknesses in the package must be quite substantial (e.g., hundreds of microns of copper in the thicker layers). FIG. 6A and FIG. 6B show respective cross-sectional and plan views of an example of the layout of a package with planar bottom source and drain contacts (e.g., suitable for surface mounting on a circuit board). In the example illustrated, the base substrate is a 500 μm (20 mil) thick copper-invar-copper (to provide a coefficient of thermal expansion [CTE] reasonably closely matched to that of the silicon die). While initially this base substrate is continuous, during processing it is sawn or etched through for electrical isolation, with the major area chosen as the source (S) package contact, while a smaller end region (the right end in FIGS. 6A and 6B) is the drain (D) package contact. The lateral current flow from the drain solder balls from the die to the drain contact end is through a thick copper layer (e.g., 250 mm [20 mils] thick plated copper in FIG. 6B). The lateral current from the source solder balls to the opposite, source contact, end of the package is through the 20 mil thick copper-invar-copper substrate, but the current reaches this substrate by passing through the 10 mil thick Cu drain plane via an array of isolated copper “studs” or “plugs” penetrating the plane.

[0175] While it would be advantageous to make the center-to-center pitch of these studs as fine as possible (e.g., the same pitch as the solder bumps on the die would be ideal), due to the 10 mil thickness of the copper layer through which they pass this is impractically difficult. In typical circuit plating processes, the aspect ratio (metal layer thickness divided by minimum horizontal feature size) is typically kept to 1:1 or less. (Higher aspect ratios can be fabricated using more exotic processes, but their higher costs would make them economically unsuitable for most applications at present.) In the package structure illustrated in FIGS. 6A and 6B, the smallest feature to be defined in the lo mil thick plated copper layer would be the narrow isolating gap (“moat”) surrounding each source plug (via) penetrating the layer. The plug itself is of reasonable dimension to carry S current vertically with low resistance, while the outer rims of the isolation moats do not get too close together or they will impede the lateral flow of drain current through this 10 mil thick plated copper drain plane. Hence, keeping the aspect ratio near 1:1, with a 10 mil thick drain plane, the nearest center-to-center stud pitch (diagonal in FIG. 6A) cannot be much less than 25-30 mils. It is advantageous in the layout to make the horizontal stud (via plug) pitch an even integer multiple of the die solder ball pitch, so for the Psb=250 μm (˜10 mil) ball pitch, a 1.000 mm (˜40 mil) horizontal stud pitch (0.7071 mm [27.84 mils] minimum [diagonal] pitch) is chosen in FIG. 6A.

[0176] While the drain plane lies directly under the drain solder balls (unless the via stud isolating moats are too large, causing some of the drain solder ball contacts to fall “off the edge” of the drain plane metal onto the moat), this is not the case for the source solder ball contacts, only a small fraction of which fall on studs. The connection of the source solder balls to the studs (via plugs) utilizes an additional layer or two of copper that is capable of being more finely patterned than the drain plane (and which hence are much thinner). This source plane metallization (seen more easily in the cross-section of FIG. 3 than in that of FIG. 6B) could have one or two layers of fineline copper about 10 μm in thickness (about {fraction (1/25)}th of the thickness of the 10 mil thick drain plane). Creating these higher density (smaller feature size) multi-layer interconnects requires a reasonably flat surface to start with, which means that the moats are filled around the plugs with a suitable dielectric material and planarize the dielectric and copper surface before the copper/BCB (or other suitable multilayer dielectric material) interconnect layer(s) are applied. While the moat diameter shown in FIG. 6A would allow drain contacting and the source plane to be created in one metal layer, in most cases it would be advantageous to have at least two fineline copper interconnect layers, both to facilitate getting the drain solder ball contacts down to the 10 mil copper drain plane and to reduce the spreading resistance from the source studs out to the majority of the source solder balls that do not sit on studs, as well as to facilitate making contact to the gate pads without significantly degrading this source plane resistance.

[0177] Alternative Wafer-Level Additive Copper/Polymer Packaging Approach

[0178] As described in the following section (Table 1), the contribution of metal resistance, both on-chip and package, to Ron can be reduced by increasing the density of solder ball contacts between the die and the package. In the packaging approach illustrated in FIGS. 3 and 6A and 6B, the solder balls (“bumps”) are fabricated directly on the completed IC wafer using standard commercial bumping processes (it is also possible to bump individual die, but wafer bumping is cheaper). While 100 μm solder bump pitches in area arrays are commercially available, the technology is not as well developed as the more common 250 μm pitch, and the reliability is problematical where significant package to silicon wafer CTE differences may exist. Also, with a 100 μm bump pitch, the need for one or two layers of “fineline” additive interconnect metal (as illustrated in FIGS. 3 and 6A and 6B) to the high-current package structure is desired in some aspects. This adds to package complexity and makes finding suitable commercial sources for the package more difficult.

[0179] The alternative packaging approach illustrated in FIG. 7 achieves the very low Ron of the 100 μm solder ball approach (or exceeds its performance) while reducing the demands on both the solder bump mating technology and the package. The concept is to fabricate the one or two (as illustrated in FIG. 7) “fineline” metal layers (e.g., 5 μm to 20 μm of copper) with polymer (e.g., BCB or polyimide) interlayer dielectric directly on the completed IC wafer in a full-wafer process. Applying the additive copper/polymer interconnects directly to the “completed” IC wafer (i.e., the wafer has passed through all of the normal fabrication steps of the CMOS IC foundry) will in general be less expensive and more practical than adding them on the package side. It is more practical because this copper/polymer technology is not generally available at package vendors. It is less expensive because of the fact that die area is smaller than that of the package; hence a smaller area of material is subjected to the cost of the copper/polymer processing when it is placed directly on the die. (In the case of very low yields of “good” die on the IC wafers, the cost of putting the “fineline” copper/polymer interconnects directly on the IC wafers could exceed that of applying them to the packages, but such low yields of good die would not be expected for mature CMOS foundry processes.)

[0180] In addition to being more practical and lower cost, applying the additive copper/polymer interconnects directly to the “completed” IC wafer offers the advantage that the density of interconnections between the normal CMOS on-chip metallization and the much thicker “fineline” copper layers is not limited by any solder bump or other joining technology, but only by the via density and metal linewidths available in the first layer of copper/polymer interconnects. The interconnect densities practical between the IC chips and an additive copper/polymer are not only much higher than solder bump densities, but there is no reliability penalty associated with going to very high via densities on a chip like there is in joining technologies such as solder bumps. In the approach of FIG. 7, there is very little Ron penalty associated with using relatively coarse solder bump (or solder stripe, etc.) pitches because the of the low sheet resistance of the additive copper layers. Hence, the solder contacts may go directly from the die (with the copper/polymer “fineline” layers on it) to very thick metal package structures having very coarse feature sizes (such as going to an interdigitated thick (e.g., >20 mils) copper-invar-copper package or some form of laminate package).

[0181] Alternative Vertical Laminate Package Approach

[0182] The package geometries illustrated in FIGS. 3 and 6A and 6B are horizontal, in that layers of metal conductors carrying the high MOSFET source and drain currents lay parallel to the surface of the MOSFET die. In this geometry, via structures carry current between the different patterned layers of package metallization. These vias (more specifically, the spreading resistance of getting currents into and out of the inter-layer via areas) represent a significant contribution to the overall package metal resistance, as well as a source of concern for package reliability. Also, the fact that the vertical thickness of the metal layers is limited by practical fabrication considerations that limit the layer thicknesses to be of the order of the horizontal feature sizes provides a further limitation on package resistance for the horizontal package geometry.

[0183] These limitations can be overcome and extremely low package resistances achieved by going to a vertical laminate package geometry, as illustrated for the case of the monolithically-integrated gate drive amplifier (FIG. 8) in FIG. 9A and 9B. In this structure, the high source and drain currents are carried in vertical metal layers (that is, perpendicular to the surface of the current switch MOSFET die). Their (horizontal) thickness is limited by the feature size of the die contacts (e.g., solder bump pitch), but their vertical extent is unlimited, so that extremely low package metal resistance levels can be achieved. Note that ordinarily, the separation of the high current paths is achieved in the vertical laminate package by sweeping, for example, the layers contacting the source rows of solder balls in one direction and those contacting the drain layers in the opposite direction (e.g., in the illustration at the bottom (FIG. 9B), the source layers might be swept in the direction into the page, and the drain layers out of the page). Alternatively, rows may be dedicated to other purposes such as low inductance Vdd connections and they can be taken out of the package bottom, in addition to the opposing sides (or either the source or drain connection could be taken out of the package bottom if desired). Note that while the attachment of this vertical laminate package directly to solder balls on die metallization pads is shown in FIG. 9B, this package configuration can also be very advantageously used with a die with the additive “fineline” thick copper interconnects added as illustrated in FIG. 7. When the additional copper/polymer interconnect layers are added to the die, the pitch of the solder contacts to the package may be greatly increased without significantly degrading Ron. This means that fewer layers of laminate are needed for the package, making it easier to match the laminate layer pitch to the solder contact pitch, and potentially making practical the use of materials like copper-invar-copper (CIC) for the metal layers in the laminate stack for improved CTE match to the silicon die, which would offer the potential for improved reliability. Note that while the use of CIC in the laminate package stack would alleviate CTE mismatch in the plane of the metal layers, there could still be CTE mismatch in the perpendicular direction due to the CTE of the organic dielectric layers in the stack. If, however, the organic dielectric interlayers are pulled back from the solder interface to the die (further than the pullback illustrated at the bottom FIG. 9B), then this perpendicular CTE mismatch may be compensated for by a small amount of bending in the laminate metal layers.

[0184] Calculated Performance for Packaged Planar Current Switching MOSFET Devices

[0185] It is of value to calculate the intrinsic device, on-chip metal, and package metal contributions to the on resistance, Ron, as well as other critical performance parameters that would be expected for a planar current switching M.NOSFET device of the type described in aspects of this invention. Since, as noted in Eq. 12, the metal interconnect resistance decreases as the density of the solder ball interconnects is increased, two cases will be presented; one assuming 125 μm balls on a 250 μm pitch (standard commercial area array solder ball practice), and the other assuming 50 μm balls on a 100 μm pitch (highest area array solder ball density that is commercially available at present). A silicon die area of 4 mm×4 mm was assumed for the planar current switching MOSFET device, so that the total number of solder balls was 256 for the 250 μm pitch or 1600 for the 100 μm pitch case. Using design rules for a commercial 2λ=0.24 μm/Leff=0.19 μm CMOS process, with a layout of the type illustrated in FIGS. 3-5D, a total FET width of 13.5 meters is achievable in the 4 mm×4 mm chip size. This process has a tox=5.8 nm gate oxide thickness which gives an N-channel resistance, Rch (Eq. 7), at Vgs=+2.5V of 43μΩ for the Leff=0.19 mm/W=13.5 m MOSFET of only 43μΩ. When the Rs=Rd=14.1μΩ source and drain resistances are added to Rch (as per Eq. 10), the intrinsic device on resistance is calculated to be only (Ron)dev=71.1 mW.

[0186] The CMOS process analyzed has a 5-layer aluminum on-chip metallization system, with metal layers M1-M4 having a resistance of 0.088Ω/sq and M5 having 0.044Ω/sq, while the S/D silicide has 4.0Ω/square. The via cut resistances are 7.5Ω/cut between the S/D silicide and M1, and 5Ω/cut between M1 and M2 or between other metal layers. While a 7.5Ω/cut S/D silicide to M1 metal layer resistance may sound serious, for a W=13.5 meter MOSFET width, there are 13.5 million of these via cuts in parallel in both the source and drain paths to share the current, so the addition to Ron is only 1.11μΩ. This parallelism applies to the other metal resistance contributions, as a consequence of a chip interconnect layout (FIGS. 4 and 5) that is well thought out to minimize metal resistance. A resistance build-up analysis of the various spreading resistances in the on-chip metal planes and the inter-layer via cut resistances gives a calculated on-chip metal resistance of 54.6μΩ in the source lead and 55.9μΩ in the drain lead (110.5μΩ total S+D) for the 250 μm solder bump pitch, which drops to 14.1μΩ in the source lead and 15.5μΩ in the drain lead (29.6μΩ total S+D) for the finer 100 μm solder bump pitch.

[0187] Similarly, the package metal resistance is also a function, though slightly less dramatic, of the solder bump pitch in the flip-chip area array interconnects between the planar current switching MOSFET die and its package. A resistance build-up analysis of the various spreading resistances in the package metal planes and through-layer “plug” resistances gives a calculated package metal resistance of 54.6μΩ in the source path and 55.9μΩ in the drain path (110.5μΩ total S+D) for the 250 μm solder bump pitch, which drops to 33.6μΩ in the source path and 46.0μΩ in the drain path (79.7μΩ total S+D) for the finer 100 μm solder bump pitch. Table 1 summarizes the contributions to the packaged device Ron (total source+drain) of the MOSFET device, the on-chip metallization, and the package metallization (including solder balls) for the “standard” (250 μm) and “high-density” (100 μm) chip-to-package solder ball array pitches.

TABLE 1
Calculated contributions to Ron for planar Leff = 0.19 μm current
switching MOSFET (Cgs + Cgd = 20 nF for W = 13.5 m,
4 mm × 4 mm die).
	Solder Ball Pitch Cases
	Standard	High-Density
	Psb = 250 μm	Psb = 100 μm
	Silicon/Transistor	71.1 μΩ	71.1 μΩ
	(Vgs = +2.5 V)
	On-Chip Metallization:	110.5 μΩ	29.6 μΩ
	Package Metal:	103.2 μΩ	79.7 μΩ
	Total Resistance	284.8 μΩ	180.4 μΩ
	(Si + Metal + Package):

[0188] Note in Table 1 that even with the high-density solder ball pitch, the largest contribution to Ron is the metallization, not the MOSFET device itself, and that the largest contribution to the Ron resistance is from the package metallization. This is a result of the fact that we have assumed a convenient planar, surface-mountable package configuration (FIGS. 6A and 6B). It would be possible to substantially reduce the package metal resistance by reducing the horizontal distance through which the source/drain current must pass between the die and the package S/D contacts. One package configuration which would accomplish this would be a vertical package geometry with the source lead on the bottom (as it is under the chip in FIG. 6B), but with the drain lead on the top, surrounding (and probably covering) the planar MOSFET die. This could be accomplished, for example, by bringing the 10 μm thick plated copper drain plane up to the surface around the die, and then using either a plated copper wall or preform to bring the contact surface above the height of the die. It would be possible to use a cover lid on this drain contact ring, or leave the back of the die exposed (with suitable underfill passivation). This configuration would reduce both the total package area and its contribution to Ron substantially, and could represent a convenient form factor for some applications.

[0189] It should be noted that the flip-chip die underfill noted above would probably be utilized in either the flat, surface-mount version of the package shown in FIGS. 6A and 6B, or in a vertical package geometry of the type just discussed. One reason for this is that underfill is an effective means of enhancing solder ball reliability in the face of differential thermal expansion between package and silicon die. Another is that the constraint provided by the underfill could be of substantial value in reducing lifetime degradation due to electromigration in the solder bump metal. The planar MOSFET die in this example should be able to switch currents of 200 amperes, even though the die is only 4 mm×4 mm in size. This pushes, however, the conventional operational current density of solder ball contacts to die for high reliability. This is not viewed as a serious concern, however, both because the constraint of the underfill should minimize the problem, and because of the way the solder balls are used in this application. In usual flip-chip reliability analyses, it is assumed that the failure of any single solder ball represents a functional failure of the part. In this planar current switching MOSFET structure, there is massive parallelism between the current-carrying (S/D) solder balls. For example, for the high-density (Psb=100 μm ball pitch) case, there will be a total of 1600 solder balls, or 800 balls in parallel in the source path and 796 balls in parallel in the drain path (assuming 4 balls for gate leads). The complete failure of even 10% or 20% of the solder balls mating the die to the package would make a barely-perceptible change in the Ron of the packaged device. (This is because the total S+D solder ball resistance contribution to the 180.4μΩ Ron value is only 8.4μΩ, and while failed balls would also locally increase the metal plane spreading resistances, the effect of even 20% randomly-distributed ball failures is very small.) The favorable statistics in this application where 10% to 20% ball failures have no significant effect, as compared to the usual “one ball failure is death” condition allows us to push to higher than normal current densities in the solder balls. Of course, if solder ball electromigration remains an issue in some applications, solder ball metal compositions more resistant to electromigration effects at the desired operating temperature can be utilized. Note that as discussed in the previous section, the alternative packaging approach of fabricating copper/polymer “fineline” interconnect layer(s) directly on the completed CMOS wafers has the advantage of achieving Ron performance at least as good as shown for 100 μm solder balls in Table 1, while using a relatively coarse feature size joining technology which should offer reliability advantages over fine-pitch solder balls.

[0190] It should be noted that whether the planar package configuration of FIGS. 6A and 6B (Ron=180.4μΩ) or the vertical package geometry (Ron=125 to 150μΩ estimated) is used, the packaged device resistances are almost unbelievably small for such a small device (4 mm×4 mm die, 12 mm×7 mm planar package, or about 6 mm×8 mm for a vertical package with the same die). Even at a 200 amp drain current, Ron=150μΩ represents only a Vds=30 mV voltage drop.

[0191] Gate Drive Requirements and Optional Device Features

[0192] A dramatic difference between the horizontal or planar geometry deep-submicron channel length current switching MOSFET structure of aspects of this invention and conventional vertical geometry power MOSFETs is in their gate drive requirements. In the example cited above, the total calculated gate capacitance is only Cgs+Cgd=20 nF (Eq. 6, with εr=3.90, L=0.24 μm, W=13.5 m and tox=5.8 nm gives Cgs+Cgd=19.28 nF). This is far (1 to 2 orders of magnitude) less than the gate capacitance of conventional vertical power MOSFETs having a comparable Ron values. (Actually, many conventional power MOSFETs connected in parallel would be required to reach this Ron level; it is the total Cgs+Cgd value for the paralleled power MOSFETs that is compared to the Cgs+Cgd=20 nF value of the planar switching MOSFET of aspects of this invention.) Also, while conventional power MOSFETs require Vgs=10 V or more gate voltages to reach low Ron, with aspects of this invention the values in Table 1 are reached with only a Vgs=2.5 V gate drive voltage. As discussed previously, the combination of the lower value of Cgs+Cgd and the lower Vgs gate drive voltage requirement drastically lowers the (Eq. 5) Pgd=½(Cgs+Cgd)ΔVgs2 Fc gate drive power requirements for the planar short-channel current switching MOSFET of aspects of this invention (by nearly a factor of 500 over conventional power MOSFETs).

[0193] One of the implications of this enormous reduction in ac gate drive power is that it becomes practical to sharply increase the switching frequency, Fc, without serious efficiency loss due. This makes it possible to reduce the size and weight of the capacitive and magnetic energy storage devices in a power converter circuit, to allow, for example, very small on-board switching power converters to be realized. For example, an Vout=1.2V switching converter having a maximum output current of 200 amperes (240 watts peak output) could be fabricated with two of these planar geometry current-switching MOSFETs, which would have, even at a very high Fc=1 MHz switching rate a total gate drive power of only Pgd=0.125 watts for the two synchronous rectifier switches, or 0.052% of the peak output power. This means that it would be quite practical to increase switching frequencies up into the many tens of megahertz range before gate drive power became a serious efficiency concern, which would allow for remarkable miniaturization of power converters.

[0194] The low gate drive power requirements, along with the fact that the planar geometry deep-submicron current switching MOSFET devices are conveniently (and inexpensively) fabricated using a standard deep-submicron CMOS foundry process, suggests a very attractive option: the inclusion of the gate driver amplifier on the same chip with the switching MOSFET. With conventional power MOSFETs, furnishing clean (“square-wave”) gate drive voltages is a major problem, even at switching frequencies of the order of Fc=100 KHz. While the planar geometry deep-submicron current switching MOSFET devices have low Cgs+Cgd=20 nF gate capacitances and are capable of operation at >10 MHz switching frequencies at low gate drive powers, for clean, efficient square-wave gate voltages the pulsed gate currents will be substantial. For example, if it is desired to keep the gate voltage risetimes and falltimes to less than 2.5% of the switching period at Fc=10 MHz, the voltage risetimes must be under tr=tf=2.5 ns. With ΔVgs=2.5V and Cgs+Cgd=20 nF, the gate drive current will pulse to ig=(Cgs+Cgd)(ΔVgs/tr)=±20 ampere levels in each MOSFET during the rise and fall intervals. The distributed inductance/characteristic impedance of usual on-board interconnects virtually precludes furnishing gate drive signals of this quality in a practical multi-package on board environment.

[0195] These gate drive signal limitations of conventional packaging can be overcome in the case of the planar geometry deep-submicron current switching MOSFET devices of aspects of this invention by placing the gate driver amplifier on the same silicon chip as the MOSFET, as illustrated in FIG. 8. The gate driver amplifier would consist of a short chain of CMOS inverters (e.g., 2 to 4 stages typically; FIG. 8 shows a 2-stage gate driver) between the gate input to the package/die and the actual MOSFET gates. In order to minimize ac gate current distribution problems, it would probably prove useful to distribute the last (largest) stage of the gate amplifier chain in sections around the chip. The sizing of the p- and n-channel MOSFET devices in the CMOS driver inverters can be estimated from the device characteristics and the desired gate drive currents. Consider a 2-stage CMOS inverter driver for the 200 ampere current switching MOSFET example, as shown in FIG. 8. The saturated drain current for the Leff=0.19 μm n-channel MOSFETs in the 2λ=0.24 μm feature size commercial CMOS foundry process is Idss/W=0.6 ma/μm with an RonW=960 μm “on” resistance. The p-channel devices are about half as good (half the Idss/W and roughly twice the RonW), so for balanced current drive the p-channel MOSFETs are scaled about twice as wide as the n-channel devices. For convenience, the sizing (width, W) of only the n-channel devices will be cited, with the understanding that, as shown in FIG. 8, the matching p-channel pull-up devices will be twice as wide. For a desired gate drive current pulse of 20 amperes into the W=13.5 meter, 200 amp current switching FET, a second-stage driver MOSFET width of Wd2=50 mm (Idss=30 amps) would more than suffice. Its Ron=0.0192Ω on resistance would give an trc=Ron(Cgs+Cgd)=0.384 ns time constant with the (Cgs+Cgd)=20 nF gate capacitance, which would give excellent gate voltage settling. The input gate capacitance, Cin2, of this Wd2=50 mm driver output stage would be about 75 pF for the n-channel device and 150 pf for the (2× wider) p-channel MOSFET, or Cin2=225 pF total. To drive this 225 pF capacitance over its ΔVgs=2.5V range in Δtr=1 ns would require Iin2=Cin2ΔVgs/Δtr=563 ma gate drive current pulses, which require that the prior first-stage driver have an n-channel MOSFET width of about Wd1=1.0 mm (Idss=600 ma). The input capacitance for this first driver stage will be about 1.5 pF for the n-channel, and 3 pF for the p-channel MOSFETs, or 4.5 pF total gate input capacitance for the chip. Since a 4.5 pF gate driver input capacitance is very easy to drive with very fast edge rates with typical Zo=50Ω characteristic impedance circuit board interconnects, the two-stage driver is more than adequate.

[0196] The inclusion of the on-chip gate driver amplifier allows the gate input of this 200 amp planar current switching MOSFET chip to be driven with remarkable timing precision with nothing more than conventional digital logic signals and circuit board interconnects. From a terminal count standpoint, it adds only two package connections; the Vdd=+2.5Vdc and Vss=ground driver amplifier power inputs. While it would be possible, in principle, in some applications to tie the input stage amplifier VSS power lead to the source lead of the current switching MOSFET, in many cases this could lead to feedback coupling problems/potential for oscillations on transitions, so a separate input stage VSS ground lead is preferred. On the other hand, the high peak gate current spikes into the switching demand a very low impedance (particularly inductance) connection between the driver output stage and the switching MOSFET gate, most easily accomplished if we tie the driver VSS power lead to the source lead of the current switching MOSFET. A side benefit to tying the VSS lead of the amplifier driver (output) stage to the source of the switching MOSFET is that it automatically achieves the “body diode” of FIG. 2B. When the input in FIG. 8 is taken “LOW” (≈VSS) to turn off the current switching MOSFET, its gate will essentially tied its source through the “ON” Wd2n=50 μm driver MOSFET. In this state, as noted in FIG. 2B, the Wn=13,500 μm current switching MOSFET will begin to conduct any time its drain voltage becomes more negative than its source by more than its gate threshold voltage, Vtn. While connecting the source of the Wd2n=50 μm n-channel driver MOSFET directly to the source of the output current switch MOSFET solves the problem for handling the large (≈20 ampere) negative gate current peaks, the equally large positive gate current spikes out of the Wd2p=100 μm p-channel driver MOSFET must also be dealt with. In the gate driver amplifier design in FIG. 8, a large (>20 nF) bypass capacitor is included between Vdd and the source of the current switching MOSFET. In the absence if this bypass capacitor, the full magnitude of the positive gate current spikes would have to be furnished through the Vdd=+2.5V gate driver amplifier supply, which would require an extremely low ac impedance (particularly inductance) to the Vdd lead in order to avoid “voltage starvation” during positive gate current transients which would compromise the switching process. The inclusion of the on-chip bypass capacitor as an extremely low inductance source of the charge required to charge the gate capacitance of the large current switching MOSFET makes an ultra-low inductance Vdd connection to the chip unnecessary. It has, however, some chip area/cost penalty. The increase in chip area due to the gate driver amplifier itself is minimal, adding a total of only Wd(n+p)=153 mm (Wd2=50 mm+Wd1=1.0 mm, or 51 mm of n-channel MOSFET width, plus twice that, or Wd1p+Wd2p=100 mm, of p-channel MOSFET width). Hence, this on-chip gate driver would require only about 1.1% of the die area. The capability for dispatching the ordinarily-odious gate drive problem at an increase of die cost of only 1% to 2% is a remarkable side-benefit of implementing the planar current switching MOSFET of aspects of this invention in a standard deep-submicron CMOS integrated circuit foundry process. The inclusion of the >20 nF bypass capacitor is more costly. Assuming the IC process has no special very high capacitance per unit area (C/A) capability (such as vertical geometry capacitors or ferroelectric dielectrics like many DRAM processes have, then the highest available C/A is the gate to channel capacitance. Implementing, using this gate oxide capacitance, a bypass capacitor whose capacitance equals the gate capacitance of the Wn=13,500 μm current switching MOSFET requires an area equal to approximately 20% of that of the Wn=13,500 μm current switching MOSFET. Again, this is a small price to pay for a virtually effortless way of solving the normally odious gate drive problem in high-speed switchers.

[0197] The capability for integrating other functionality on the current-switching MOSFET die by including CMOS circuitry of various types is also enabled by the use of a CMOS IC process for fabricating the devices. These could include various types of analog or digital circuitry that would otherwise require separate IC chips in the various applications. One example of this would be the inclusion of the switcher control circuitry for a power converter (i.e., the analog circuitry that compares the actual VOUt dc output voltage of the converter to the voltage setpoint value and generates the various primary switching and secondary output synchronous rectifier switching timing signals needed for the operation of the power converter. While this would require additional package pins, the value added in reduced parts count and potential for miniaturization would be substantial. Another example, shown in FIG. 2b, would be the inclusion of the “optional ultra-low Qd diode” to replace the “body diode” (FIG. 2a) of a normal vertical-geometry power MOSFET. This “body diode” function is emulated by an active diode-connected p-channel MOSFET (i.e., the gate is connected to the drain). This device structure and its applications were discussed in a previous section. Note that it is possible to include both the gate driver amplifier and active diode-connected p-channel MOSFET “body diode” options at the same time (i.e., as additions to the same planar current switching MOSFET die), as could be other application-specific circuitry. Other applications for the planar current switching MOSFET devices of aspects of this invention could benefit from the addition of specialized circuitry designed to serve the needs of each particular application.

FIGURE CAPTIONS

[0198] FIG. 1 a . [Top] Device structure of a conventional vertical geometry power MOSFET showing lateral electron path through surface n-channel transitioning to vertical path down to drain contact.

[0199] FIG. 1 b . [Bottom] Device structure of n-channel planar/horizontal geometry high-current switching MOSFET of aspects of this invention implemented in a deep-submicron CMOS IC process, showing very short lateral electron path for very low Ron. Also illustrated at right is the capability to include p-channel MOSFETs on same die.

[0200] FIG. 2 a . [Left] Equivalent circuit for conventional vertical geometry n-channel MOS power FET device, showing body diode. Note that very large stored diffusion charge, Qd, in body diode severely limits switching speeds at which it can be used.

[0201] FIG. 2 b . [Right] Equivalent circuit for planar/horizontal geometry power high-current switching MOSFET of aspects of this invention, including optional ultra-low stored charge diode implemented with an active diode-connected p-channel MOSFET for use when “body diode” functionality is required.

[0202] FIG. 3. Cross-section drawing of planar deep-submicron current switching MOSFET of aspects of this invention including high-current die and package interconnects from source and drain electrodes. Die features are drawn to scale for a 2λ=0.24 μm feature size CMOS process, but some package/solder ball dimensions reduced to maintain visibility of die features.

[0203] FIGS. 4A-4B. Plan view of layout example for planar deep-submicron current switching MOSFET of aspects of this invention drawn to scale for implementation in a 2λ=0.24 μm feature size CMOS process. The source/drain and gate poly silicide layers plus the via cuts (small squares) up to the first level metal (Ml) are illustrated at the upper left. At the upper right, M1, the first level of interconnect metal, is added, and the via cuts to M2 are shown. At the lower left, M2, the second level of interconnect metal, is added, and the via cuts to M3 are shown. At the lower right, M3, the third level of interconnect metal, dedicated principally to the source plane, is added, and the via cuts to M4 are shown.

[0204] FIGS. 5A-5B. (Continued from FIG. 4). Plan view of layout example for planar deep-submicron current switching MOSFET of aspects of this invention drawn to scale for implementation in a 2λ=0.24 μm feature size CMOS process. At the upper left, M3 and the via cuts to M4 are shown, as in FIG. 4D. At the upper right, M4, the fourth level of interconnect metal, dedicated principally to the drain plane, is added, and the via cuts to M5 are shown. At the lower left, M5, the fifth and final level of interconnect metal, used principally for the source, drain and gate solder ball pads and gate interconnect lines, is added (the scale does not permit showing the “pad mask” dielectric opening that defines the circular solder ball contact areas). At the lower right, the scale has been changed to show the entire 4 mm×4 mm die, showing the M5 (top metal) source, drain and gate solder ball pads with gate interconnect lines running in between them, and the “pad mask” dielectric opening that defines the circular solder ball contact areas.

[0205] FIGS. 6A and 6B. Plan view [top] and cross-sectional view [bottom] of example of a planar package for the planar deep-submicron current switching MOSFET of aspects of this invention. Because the high current (e.g., 200 amp) source and drain leads are coplanar on the package bottom (as well as the ends of the top surface), it would be suitable for surface mount applications (with an appropriate gate lead extension from the gate pad on the top surface).

[0206] FIG. 7. Example of including optional two CMOS inverter stage gate driver amplifier on the same die as a 200 amp planar deep-submicron current switching MOSFET of aspects of this invention. The driver-amplifier would be capable of supplying 20 to 30 amp gate pulses to the W=13,500 m [(Cgs+Cgd)=20 nF] planar switching MOSFET for 1.5 to 2 ns risetimes of the 0 to 2.5V gate voltage, while presenting only about a 4.5 pF capacitive load at the package gate input and requiring less than 1.5% to 2% of the die area.

[0207] FIG. 8. Example of a gate driver amplifier.

[0208] FIGS. 9A and 9B. Example plan and side views of a vertically laminated package.

[0209] FIG. 10. 250 μm Bump Pitch Calculation of 0.19 μm Power Switching FET Resistance with On-Chip Metal and Package R.

Claims

1. Integrated circuitry comprising: a monolithic semiconductive substrate; a power semiconductor switching device comprising a plurality of field effect transistors formed using the monolithic semiconductive substrate and having a plurality of electrical contacts including a plurality of gate contacts, a plurality of source contacts coupled in parallel and a plurality of drain contacts coupled in parallel; and auxiliary circuitry formed using the monolithic semiconductive substrate and configured to couple with at least one of the electrical contacts of the power field effect transistors.

2. The circuitry of claim 1 wherein the field effect transistors comprise planar field effect transistors.

3. The circuitry of claim 1 wherein the auxiliary circuitry comprises a gate driver amplifier configured to provide a control signal to the electrical contacts of the field effect transistors comprising the gate contacts.

4. The circuitry of claim 1 wherein the auxiliary circuitry comprises a power converter controller configured to provide a control signal to the electrical contacts of the field effect transistors comprising the gate contacts.

5. The circuitry of claim 1 wherein the gate contacts are coupled in parallel.

6. The circuitry of claim 1 wherein the auxiliary circuitry comprises an application specific integrated circuit.

7. The circuitry of claim 1 wherein the auxiliary circuitry comprises a zero-current switching/timing circuit.

8. The circuitry of claim 1 wherein the auxiliary circuitry comprises a load protection circuit.

9. The circuitry of claim 1 wherein the auxiliary circuitry comprises an active snubber circuit.

10. The circuitry of claim 1 wherein the power semiconductor switching device and the auxiliary circuitry are formed upon a die.

11. The circuitry of claim 1 wherein the field effect transistors comprise MOSFET devices.

12. A method of forming a power transistor comprising: providing a monolithic semiconductive substrate having a surface; forming a power field effect transistor using the monolithic substrate and having a source contact and a drain contact adjacent to the surface; and forming auxiliary circuitry using the monolithic semiconductive substrate, the forming comprising coupling the auxiliary circuitry with at least one contact of the power field effect transistor.

13. The method of claim 12 wherein providing comprises providing the substrate comprising a semiconductor die.

14. The method of claim 12 wherein the forming the power field effect transistor comprises forming a plurality of planar field effect transistors electrically coupled in parallel.

15. The method of claim 12 wherein the forming auxiliary circuitry comprises forming a gate driver amplifier configured to provide a control signal to a gate contact of the power field effect transistor.

16. The method of claim 12 wherein the forming auxiliary circuitry comprises forming a power converter controller configured to provide a control signal to a gate contact of the power field effect transistor.

17. The method of claim 12 wherein the forming auxiliary circuitry comprises forming the auxiliary circuitry comprising application specific integrated circuitry.

18. The method of claim 12 wherein the formings individually comprise forming the power field effect transistor and the auxiliary circuitry comprising CMOS devices.

19. The method of claim 12 wherein the forming auxiliary circuitry comprises forming the auxiliary circuitry comprising zero-current switching timing circuitry.

20. The method of claim 12 wherein the forming auxiliary circuitry comprises forming the auxiliary circuitry comprising active snubber circuitry.

21. The method of claim 12 wherein the forming auxiliary circuitry comprises forming the auxiliary circuitry comprising load protection circuitry.

22. The method of claim 12 wherein the forming the power field effect transistor comprises forming a plurality of MOSFET devices.