Patent Application
20130237055
The present invention relates to a method of redistributing or rewiring a functional element, and more particularly to a method of redistributing or rewiring a functional element that can reduce influence of stress produced in an internal element during a surface flattening process.
Recent functional elements have been miniaturized with improved performance and advanced functions. A redistribution conductive layer has been added to a miniaturized functional element in order to rewire the functional element and to achieve a higher packaging density. Thus, size reduction of electronic equipment has been achieved. It is to be noted throughout the instant specification that the term “redistributing” is used to specify rewiring for repetition of wiring.
The following patent documents disclose a method of redistributing or rewiring a functional element. For example, Japanese Patent No. 4057146 and Japanese laid-open patent publication No. 2007-53395 disclose that pillars or gold projecting electrodes are formed with a predetermined height on an electrode pad formed on an underlying substrate and on an electrode pad of a semiconductor device mounted on the substrate. Then an insulating resin layer is provided on the entire surface of the structure. Thereafter, the copper (Cu) pillars or the gold projecting electrodes that have been covered with the insulating resin layer is polished such that only upper portions of the pillars and the projecting electrodes are exposed so as to serve as a terminal. In a subsequent process, an interconnection conductive layer is formed on the insulating resin layer by using an electrolytic plating method such that it is connected to the exposed gold or copper terminals.
For example, according to Japanese laid-open patent publication No. 2008-300559, an insulating resin layer is formed after a semiconductor device has been mounted on an underlying substrate. Via holes are formed in the insulating resin layer on an electrode pad. An interconnection conductive layer is formed on upper surfaces of the electrode pad and the insulating resin layer by an electrolytic plating method or the like.
However, the aforementioned technology disclosed in the patent documents has the following problems. A first problem is that stress is applied to a circuit layer within a semiconductor device during a surface flattening process. As a result, a low-k layer (interlayer dielectric having a low dielectric constant) is broken. For example, according to Japanese Patent No. 4057146 and Japanese laid-open patent publication No. 2007-53395, an insulating resin layer includes therein copper (Cu) pillars or gold projecting bumps on an electrode pad of a semiconductor device. The electrode that has been covered with the insulating resin is polished such that only an upper portion of the electrode is exposed so as to serve as a terminal. At that time, as shown in a cross-sectional structure of
A second problem is that the manufacturing yield is lowered by open defects produced after the formation of the interconnection conductive layer because a seed layer is discontinuously formed at some locations. For example, according to Japanese laid-open patent publication No. 2008-300559, some steps are produced on a surface of an insulating resin layer around a location at which a semiconductor device has been located. This becomes significant when a resin is supplied by a spin coating method. Accordingly, when an interconnection is formed with a width of 20 μm or less and a thickness of 20 μm or less, patterning defects are likely to occur in exposure and development of a photoresist, resulting in a lowered manufacturing yield. Furthermore, if a via hole has a small inside diameter of 30 μm or less and an aspect ratio higher than 1, a seed layer is likely to be formed discontinuously on a side wall and a bottom of the via hole at the time of supply of the plating seed layer. Thus, the manufacturing yield is problematically lowered by open defects produced after the formation of the interconnection conductive layer.
The present invention has been made in view of the above problems. It is, therefore, an object of the present invention to obtain surface flatness of an insulating resin, which is effective in formation of an interconnection conductive layer, by using a polishing or grinding process. Another object of the present invention is to provide a product that can prevent damage to an internal interconnection structure of a functional element due to application of stress and can have high reliability and yield.
According to one aspect of the present invention, there is provided a method of redistributing a functional element, the method comprising:
a first step of forming an insulating layer on a functional element and then forming a via hole in the insulating layer for thereby forming a via hole on an electrode pad of the functional element;
a second step of filling the via hole with a sacrificial layer;
a third step of flattening a surface above the functional element so as to expose the sacrificial layer in the via hole;
a fourth step of removing the sacrificial layer in the via hole so as to expose the electrode pad in the via hole; and
a fifth step of connecting a interconnection conductive layer to the exposed electrode pad in the via hole.
According to another aspect of the present invention, there is provided a method of redistributing a functional element, the method comprising:
a first step of forming at least one interconnection layer on a base substrate;
a second step of mounting a functional element on the base substrate;
a third step of forming an insulating layer on the base substrate including the mounted functional element and then forming a via hole in the insulating layer for thereby forming a via hole on an electrode pad of the functional element;
a fourth step of filling the via hole with a sacrificial layer;
a fifth step of flattening a surface above the functional element so as to expose the sacrificial layer in the via hole;
a sixth step of removing the sacrificial layer in the via hole so as to expose the electrode pad in the via hole; and
a seventh step of connecting a interconnection conductive layer to the exposed electrode pad in the via hole.
According to another further aspect of the present invention, there is provided a method of redistributing a functional element, the method comprising:
a first step of forming a sacrificial layer pillar on an electrode pad of a functional element;
a second step of forming an insulating layer on an entire surface of the functional element including the sacrificial layer pillar;
a third step of flattening a surface of the insulating layer so as to expose the sacrificial layer pillar;
a fourth step of removing the exposed sacrificial layer pillar so as to form a via hole on the electrode pad; and
a fifth step of connecting an interconnection conductive layer to the electrode pad of the functional element via the via hole.
According to another further aspect of the present invention, there is provided a method of redistributing a functional element, the method comprising:
a first step of forming at least one interconnection layer on a base substrate;
a second step of forming a sacrificial layer pillar on an electrode pad of a functional element;
a third step of mounting the functional element on which the sacrificial layer pillar has been formed on the base substrate;
a fourth step of forming an insulating layer on the base substrate so as to cover the mounted functional element;
a fifth step of flattening a surface of the insulating layer so as to expose the sacrificial layer pillar;
a sixth step of removing the exposed sacrificial layer pillar so as to expose the electrode pad; and
a seventh step of connecting a interconnection conductive layer to the exposed electrode pad of the functional element.
According to a method of redistributing a functional element of the present invention, an insulating layer is supplied onto a functional element. A flattening process is performed in a state in which a portion to be a via hole on an electrode pad of the functional element has been filled with a sacrificial layer. Then a conductive layer for redistribution that is connected to the electrode pad of the functional element is formed. According to the present invention, the sacrificial layer relaxes shearing stress applied to the electrode pad during a flattening process of polishing or grinding. Therefore, it is possible to prevent damage to an internal interconnection of the functional element. Accordingly, it is possible to prevent breakage of a brittle material such as a low-k material in the functional element, which would be caused by transmission of shearing stress when conventional pillars or gold projecting electrodes are used. A fine interconnection conductive layer can be formed with a high level of flatness after removal of the sacrificial layer. Thus, it is possible to obtain a method of redistributing a functional element that has excellent reliability and a high yield.
a) to 1(e) are schematic cross-sectional views (Part 1) of processes showing a manufacturing method according to a first embodiment of the present invention.
f) to 1(j) are schematic cross-sectional views (Part 2) of processes showing the manufacturing method according to the first embodiment of the present invention.
a) to 2(e) are schematic cross-sectional views (Part 1) of processes showing a manufacturing method according to a second embodiment of the present invention.
f) to 2(j) are schematic cross-sectional views (Part 2) of processes showing the manufacturing method according to the second embodiment of the present invention.
a) to 3(d) are schematic cross-sectional views (Part 1) of processes showing a manufacturing method according to a third embodiment of the present invention.
e) to 3(h) are schematic cross-sectional views (Part 2) of processes showing the manufacturing method according to the third embodiment of the present invention.
a) to 4(d) are schematic cross-sectional views (Part 1) of processes showing a manufacturing method according to a fourth embodiment of the present invention.
e) to 4(f) are schematic cross-sectional views (Part 2) of processes showing the manufacturing method according to the fourth embodiment of the present invention.
A semiconductor having an interconnection formed on silicon (Si), gallium arsenide (GaAs), lithium tantalate (LiTaO3), lithium niobate (LiNbO3), crystal, or the like, a microelectromechanical system, which is hereinafter abbreviated to MEMS, a surface acoustic wave (SAW) filter, a thin film functional element, and the like, a printed board such as a condenser, a resistance, or an inductor, and a flexible substrate having an interconnection formed thereon are suitably used for a functional element according to the present invention. However, the functional element is not limited to those specific examples. A functional element, a semiconductor such as silicon, glass, alumina, glass-ceramic, ceramic such as titanium nitride or aluminum nitride, metals such as copper, stainless, iron, and nickel, and an organic resin such as a polyimide sheet or an epoxy sheet are suitably used for the base substrate. However, the base substrate is not limited to those specific examples.
A UV-YAG laser, a CO2 laser, and the like are suitably used to open a via hole in an insulating resin layer. However, the method of opening the via hole is not limited to those specific examples. When the insulating resin layer is photosensitive, the via hole can be opened by exposure and development. Furthermore, the via hole can also be opened by dry etching.
According to the present invention, copper (Cu), nickel (Ni), gold (Au), silver (Ag), tin-silver (Sn—Ag) solder, and the like are used for portions of an interconnection conductive layer that are exposed on a surface thereof. For example, even if an interconnection conductive layer is formed by using copper-plating, the interconnection conductive layer can suitably be formed by formation of a seed layer deposited by electroless plating or sputtering, together with an electrolytic plating process, a printing process, a reflow process, and the like. However, the material of the surface of the interconnection conductive layer is not limited to those specific examples. Copper, nickel, gold, silver, and Sn—Ag are also suitably used for metal pillars located near a side surface of the mounted functional element. However, the material of the metal pillars is not limited to those specific examples. Metal pillars can be formed by plating. After conductive paste is printed, a high-temperature treatment may be performed to integrally form metal within the via hole.
Furthermore, a solder resist layer having openings formed only at necessary locations can suitably be formed on the uppermost surface of a circuit board including a functional element according to the present invention. Since the necessary locations are covered with the solder resist layer, it is possible to regulate interconnection conductive portions exposed on a surface of the structure, to prevent oxidation of interconnections, and to prevent a short circuit between conductive electrode interconnections at the time of mounting with a solder. Furthermore, it is possible to form an interconnection conductive layer that can prevent oxidation and has high solder wettability when soldering with copper, nickel, gold, silver, Sn—Ag, or the like, electroless plating, electrolytic plating, printing, or the like is conducted on the interconnection conductive layer exposed in the openings.
A buildup in which insulating layers and interconnection conductive layers are alternately formed on opposite surfaces in such a state that the interconnection conductive layers are connected to each other by a via hole for multilayered interconnections can be formed in a substrate including a functional element according to the present invention. The present invention covers such a multilayered circuit board including a functional element, an electronic part mounted to another circuit board or functional element after individual dicing, and a substrate having such a substrate including a functional element.
Embodiments of the present invention will be described in detail with reference to the drawings.
a) shows a structure of a functional element 1, an internal interconnection layer 2 of the functional element, and electrode pads 3 provided on the uppermost portion of the internal interconnection layer 2. In
c) shows a subsequent step of forming via holes 5 in the insulating layer 4. The via holes 5 are formed so that part of the electrode pads 3 is exposed. In a case where the insulating layer 4 is made of a photosensitive material, the via holes 5 are suitably formed by exposure and development. In a case where the insulating layer 4 is made of a non-photosensitive material, the via holes 5 are suitably formed by using a resin mask or a metal mask and dry-etching or wet-etching using a solvent or the like. However, the method of forming the via holes 5 is not limited to those specific examples. The irregularities generated in
In a subsequent process of
A buffing machine, a grinder, a surface planer (grinding machine or cutting machine), a chemical mechanical polisher (CMP), and the like are suitably used as a polishing or grinding device in the flattening step of flattening the surfaces of the sacrificial layer 6 and the insulating layer 4. However, the polishing or grinding device is not limited to those specific examples. Those machines are selected depending upon the grinding thickness, the allowable height control precision, the allowable surface roughness, and contents of the sacrificial layer 6 and the insulating layer 4. According to the present invention, the filled sacrificial layer 6 relaxes shearing stress applied to the electrode pads 3 in the polishing or grinding process. Therefore, it is possible to prevent damage to an internal interconnection of the functional element 1. Accordingly, the yield and the reliability of the product can be enhanced.
Subsequently, the sacrificial layer 6 filled in the via holes 5 is removed so that the via holes 5 are opened in the cross-sectional structure of
g) shows a cross-sectional structure in which, after a seed layer 7 is supplied onto the structure of
j) is a schematic cross-sectional view showing that an insulating layer 25 and an interconnection conductive layer 26 are formed for further multilayering by using a semi-additive method after the formation of the conductive layer for redistribution according to the present invention in
According to a redistribution method of the present embodiment, an insulating layer is formed on a functional element, and a via hole is defined in the insulating layer on an electrode pad of the functional element. In a state in which the via hole has been filled with a sacrificial layer, the insulating layer and the sacrificial layer are flattened. The sacrificial layer in the via hole is removed. An interconnection conductive layer is formed so that the via hole is filled with the interconnection conductive layer. Thus, a redistribution or rewiring conductive layer is formed. Thereafter, an insulating layer and an interconnection conductive layer may alternately be formed so as to provide a multilayered interconnection. Furthermore, a solder resist, a metal bump, or the like may be formed for a final product.
In a polishing or grinding process according to the present invention, a relaxation layer relaxes shearing stress applied to the electrode pad. Therefore, it is possible to prevent damage to an internal interconnection of the functional element. Accordingly, it is possible to provide a functional element product having excellent yield and reliability.
a) to 2(e) and 2(f) to 2(j) are schematic cross-sectional views showing processes of a manufacturing method according to a second embodiment of the present invention.
a) shows a structure in which, after an interconnection layer 12 is formed on a base substrate 11, metal pillars 13 are formed on the interconnection layer 12. Metals such as Cu and stainless, glass substrates, alumina substrates, Si, and the like are suitably used for the base substrate according to the present invention. However, the material of the base substrate is not limited to those specific examples. Furthermore, from the viewpoint of electric characteristics, it is preferable to provide an insulating layer between the base substrate 11 and the interconnection layer 12 in a case where the base substrate 11 is a conductor or a semiconductor. In a case where the base substrate 11 is a functional element, the metal pillars 13 provided right above electrode pads via the interconnection layer 12 may cause damage to the interior of the functional element. Therefore, it is not preferable to provide the metal pillars 13 right above the electrode pads from the viewpoint of a subsequent grinding or polishing process. In such a case, the positions of the electrode pads are deviated from the interconnection layer 12 so that the electrode pads do not overlap the metal pillars. Copper, gold, Sn—Ag, Sn, and the like are suitably used for the metal pillars 13. However, the material of the metal pillars 13 is not limited to those specific examples. A method of forming a projecting electrode by plating or heating a gold wire, printing of metal paste, a reflow method, and the like are suitably used as a method of manufacturing the metal pillars 13. However, the method of manufacturing the metal pillars 13 is not limited to those specific examples.
b) shows a structure in which a functional element 15 is provided at a predetermined position in the structure of
c) shows a structure obtained by supplying an insulating layer 17 on the structure of
d) is a schematic view showing a cross-sectional structure in which an insulating layer 18 is supplied onto an upper surface of the structure shown in
e) is a schematic cross-sectional view showing that a sacrificial layer 20 is supplied to the structure of
f) is a schematic view showing a cross-sectional structure in which the structure of
g) is a schematic cross-sectional view showing that the sacrificial layer 20 filled in the via holes 19 on the electrode pads 16 of the functional element 15 is removed from the structure of
h) is a schematic view showing a cross-sectional structure in which a seed layer 21 for a plating process and a photoresist layer 22 for portions that are not to be plated are formed on the structure of
i) is a schematic view showing a cross-sectional structure in which an interconnection conductive layer 23 is formed on the structure shown in
j) is a schematic view showing a cross-sectional structure in which, after the photoresist 22 is removed from the structure shown in
A method of redistributing a functional element according to the present invention covers a case where the interconnection conductive layer on the base substrate or on the functional element is multilayered, a case where the base substrate is removed, and a case where the base substrate is packaged. Furthermore, the metal pillars are not required if the interconnection layer and the interconnection conductive layer do not need to be connected electrically to each other. The present invention covers the case where no metal pillars are formed.
According to a redistribution method of the present embodiment, an interconnection layer is formed on a base substrate. A metal pillar or a functional element is arranged on the interconnection layer. An insulating layer is formed on the base substrate including the arranged functional element. The insulating layer is removed around the functional element. Furthermore, an insulating layer is formed. A via hole is formed above an electrode pad of the functional element. The insulating layer and a sacrificial layer are flattened in a state in which the via hole is filled with the sacrificial layer. Then the sacrificial layer within the via hole is removed, and an interconnection conductive layer is formed so that the via hole is filled with the interconnection conductive layer. Thus, a redistribution conductive layer is formed. In a polishing or grinding process according to the present invention, a relaxation layer relaxes shearing stress applied to the electrode pad. Therefore, it is possible to prevent damage to an internal interconnection of the functional element. Accordingly, it is possible to provide a functional element product having excellent yield and reliability.
a) to 3(d) and 3(e) to 3(h) are schematic cross-sectional views showing processes of a manufacturing method according to a third embodiment of the present invention.
a) shows a structure which includes a functional element 31, an internal interconnection layer 32 of the functional element, and electrode pads 33 provided on the uppermost layer of the internal interconnection layer 32. In
In
In a subsequent process of
Subsequently, the sacrificial layer pillars 34 are removed by a solvent or a chemical liquid such that via holes 36 are formed as shown in a cross-sectional structure of
f) shows a cross-sectional structure in which, after a seed layer 37 is formed on the structure of the
Subsequently, opened portions of the photoresist layer 38 are plated with a metal conductor having a desired thickness by an electrolytic plating method or an electroless plating method. Thus, an interconnection conductive layer 39 is formed as shown in a cross-sectional structure of
According to a redistribution method of the present embodiment, a sacrificial layer pillar is formed on an electrode pad of a functional element. Furthermore, an insulating layer is formed on the entire surface of the functional element. The insulating layer and the sacrificial layer pillar are flattened. Then the sacrificial layer pillar is removed so as to form a via hole. An interconnection conductive layer is formed so that the via hole is filled with the interconnection conductive layer. Thus, a redistribution conductive layer is formed. In a polishing or grinding process according to the present invention, relaxation layer pillars, namely, sacrificial layer pillars relax shearing stress applied to the electrode pad. Therefore, it is possible to prevent damage to an internal interconnection of the functional element.
Accordingly, it is possible to provide a functional element product having excellent yield and reliability.
a) to 4(d) and
a) shows a structure in which, after an interconnection layer 42 is formed on a base substrate 41, metal pillars 43 are formed on the interconnection layer 42. Metals such as Cu and stainless, glass substrates, alumina substrates, Si, and the like are suitably used for the base substrate according to the present invention. However, the material of the base substrate is not limited to those specific examples. Furthermore, from the viewpoint of electric characteristics, it is preferable to provide an insulating layer between the base substrate 41 and the interconnection layer 42 in a case where the base substrate 41 is a conductor or a semiconductor. In a case where the base substrate 41 is a functional element, the metal pillars 43 provided right above electrode pads via the interconnection layer 42 may cause damage to the interior of the functional element. Therefore, it is not preferable to provide the metal pillars 43 right above the electrode pads from the viewpoint of a subsequent grinding or polishing process. Copper, gold, Sn—Ag, Sn, and the like are suitably used for the metal pillars 43. However, the material of the metal pillars 43 is not limited to those specific examples. A method of forming a projecting electrode by plating or heating a gold wire, printing of metal paste, a reflow method, and the like are suitably used as a method of manufacturing the metal pillars 43. However, the method of manufacturing the metal pillars 43 is not limited to those specific examples.
b) shows a structure in which a functional element 45 is provided at a predetermined position in the structure of
c) shows a structure obtained by supplying an insulating layer 48 on the structure of
d) is a schematic view showing a cross-sectional structure in which an insulating layer 49 is supplied onto an upper surface of the structure shown in
e) is a schematic view showing a cross-sectional structure in which the tops of the metal pillars 43 and the tops of the sacrificial layer pillar 47 on the electrode pads 46 of the functional element 45 are exposed in the structure showing in
f) is a schematic cross-sectional view showing that the sacrificial layer pillars 47 on the electrode pads 46 of the functional element 45 are removed from the structure shown in
The schematic cross-sectional view of
According to a redistribution method of the present embodiment, an interconnection layer is formed on a base substrate. A metal pillar or a functional element having a sacrificial layer pillar formed on an electrode pad is arranged on the interconnection layer. An insulating layer is formed on the base substrate on which the functional element has been arranged. The insulating layer is removed around the functional element. Furthermore, an insulating layer is formed. The insulating layer, the sacrificial layer pillar, and the metal pillar are flattened, and the sacrificial layer pillar on the electrode pad is removed. Then an interconnection conductive layer is formed so that a via hole from which the sacrificial layer pillar has been removed is filled with the interconnection conductive layer. Thus, a redistribution conductive layer is formed. In a polishing or grinding process according to the present invention, a relaxation layer pillar relaxes shearing stress applied to the electrode pad. Therefore, it is possible to prevent damage to an internal interconnection of the functional element. Accordingly, it is possible to provide a functional element product having excellent yield and reliability.
A first example of the present invention will be described in detail with reference to the drawings. The details of the first example will specifically be described with reference to
a) is a cross-sectional view showing a structure in which an LSI of a Si substrate was used as a functional element 1 and electrode pads 3 of aluminum (Al) were provided on the uppermost layer of a BEOL layer (Back End Of Line) formed at portions at which transistors were formed, which corresponded to an internal interconnection layer 2 of the functional element 1. The BEOL layer includes a low-k material therein. In a subsequent process, an insulating layer 4 was formed as shown in
c) shows a structure in which via holes 5 were formed in the insulating layer 4 in the subsequent process. In the case where the insulating layer 4 is formed of BCB, the via holes 5 can be formed by exposure and development. In view of photosensitive characteristics, a smaller film thickness of resin is effective to form finer via holes 5. The irregularities on the insulating layer 4, which had been produced in the state of
Subsequently, in the process of
The sacrificial layer 6 was ground or polished by a predetermined thickness so as to remove an upper surface of the sacrificial layer 6 such that the remaining BCB had a thickness of 5 μm. Thus, the upper surface was flattened as shown in
The sacrificial layer 6 is formed of resin (resist) and is not formed of metal. Therefore, the hardness of the sacrificial layer 6 is low. Thus, the stress produced during the grinding is relaxed and absorbed by the sacrificial layer 6. Accordingly, the stress produced during the grinding is not transmitted to the interior of the functional element. As a result, it is possible to prevent damage to an internal circuit of the functional element due to the stress. Furthermore, because an abrasive wear of a tip of the grinder (diamond tool) 106 can be reduced, the number of products to be processed by one grinder can be increased. Thus, it is possible to reduce cost for manufacturing products. If the surface roughness is required to be further lowered, the surface is planarized by CMP so as to obtain the surface roughness Rmax of 0.5 μm or less.
Subsequently, the sacrificial layer 6 filled in the via holes 5 was removed so that the via holes 5 were opened as in the cross-sectional structure of
Next, as shown in the schematic cross-sectional view of
Then, by an electrolytic plating method, opened portions of the photoresist layer 8 were plated with copper having a thickness of 1 μm to 30 μm to thereby form an interconnection conductive layer 9, resulting in the cross-sectional structure of
Thereafter, a solder resist layer was supplied by a laminator, and Sn solder plating was conducted. The wafer was diced so as to produce individual pieces of LSIs on which redistributed interconnections had been formed. According to the present invention, multiple layers of insulating layers and interconnection conductive layers can alternately be formed so as to form a multilayered interconnection. The above method provided a functional element product having excellent reliability.
j) is a schematic cross-sectional view showing that an insulating layer 25 and an interconnection conductive layer 26 were formed for further multilayering by using a semi-additive method after the formation of the redistributed interconnections according to the present invention in
According to a method of redistributing a functional element in this example, an insulating resin layer is supplied onto a functional element wafer such as an LSI. The resin on an electrode pad is removed by a dry etching process, a photosensitive process, or a laser, thereby forming a via hole. Subsequently, the interior of the via hole is filled with a sacrificial resin by a spin coating method, a printing method, or a laminating method. Then the top of the insulating resin is exposed by grinding or polishing. At that time, since resin is present on the electrode pad, it is possible to prevent separation produced between the insulating resin and a Cu pillar or between the insulating resin and a gold projecting electrode or breakage of a low-k material, which would be caused by transmission of shearing stress when a conventional pillar or a conventional gold projecting electrode is used. Simultaneously, it is possible to prevent grinding wastes from entering into the via hole. Furthermore, a surface of the insulating resin layer is flattened. Then the sacrificial layer resin within the via hole is removed by a solvent, heat, or UV radiation. A plating seed layer is formed, and a plating resist pattern is formed. Then electrolytic plating is conducted. At that time, a fine interconnection pattern can be formed on a flat surface of the resin around the via hole. The resist is removed, and the seed layer is etched. Thus, a redistribution layer is formed from the electrode pad.
According to a method of redistributing a functional element in this example, a sacrificial layer of a resist is present on an electrode pad during a grinding or polishing process. Therefore, shearing stress can be relaxed so as to prevent damage of an internal circuit of the functional element. Thus, it is possible to form a fine interconnection conductive layer that can prevent breakage of the interior of the functional element, has excellent reliability and a high yield, and can achieve a high level of flatness.
A second example of the present invention will be described in detail with reference to the drawings. The details of the second example will specifically be described with reference to
a) is a view showing a structure in which, after a copper interconnection layer 12 was formed on a base substrate 11 with a thickness of 1 μm to 5 μm, Cu metal pillars 13 were formed on the interconnection layer 12 with a height of 10 μm to 50 μm. An 8-inch wafer or a 12-inch wafer of Si having a SiO2 layer formed between the interconnection layer 12 and the wafer was used as the base substrate. In a case where transistors are also formed inside of the base substrate, a design in which metal (Cu) pillars 13 are formed right above the electrode pads via the interconnection layer 12 is avoided such that damage of the base substrate can be prevented in a subsequent grinding process.
Subsequently, a functional element 15 having a thickness of 8 μm to 20 μm was mounted on a predetermined location of the interconnection layer 12, at which an alignment mark had been formed on the structure of
For heat radiation, the copper interconnection layer 12 was formed right below the functional element being mounted, so that heat was diffused into a wide area on the base substrate. For elements having a low calorific value, such as an IPD, no interconnection layer 12 was formed between the base substrate 11 and the adhesive layer 14. Thus, the base substrate 11 may be connected directly to the functional element 11 via the adhesive layer 14. At that time, electrode pads 16 of the functional element 15 were exposed upward. The adhesive layer 14 was supplied onto the base substrate 11 by a spin coating method. BCB made by the Dow Chemical Company for removing resin at locations other than locations requiring an adhesive by exposure and development or the LE series made by Lintec Corporation with a thickness of 15 μm that had been laminated on a rear face of the functional element 15 being mounted was used for the adhesive layer 14. The adhesive was selected depending upon the thickness of the functional element and the thickness of the Cu pillars.
c) is a view showing that, after an insulating layer 17 was supplied onto the structure of
If the resin has a low viscosity and the functional element has a thickness of 10 μm or larger, the structure of
d) is a schematic view showing a cross-sectional structure in which an insulating layer 18 was supplied onto an upper surface of the structure of
e) is a schematic cross-sectional view showing that a sacrificial layer 20 was supplied onto the structure shown in
f) is a schematic view showing a cross-sectional structure in which the tops of the Cu pillars 13 and the tops of the sacrificial layer 20 filled in the via holes 19 above the electrode pads 16 of the functional element 15 were exposed by grinding or polishing the structure shown in
According to the present invention, the filled sacrificial layer 20 relaxes shearing stress applied to the electrode pads 16 in the polishing or grinding process. Therefore, it is possible to prevent damage to an internal interconnection of the functional element 15. Accordingly, the yield and the reliability of the product can be enhanced.
g) is a schematic cross-sectional view showing that the sacrificial layer 20 filled in the via holes 19 on the electrode pads 16 of the functional element 15 was wet-etched with MEK, ethanol, IPA, or the like in the structure of
h) is a schematic view showing a cross-sectional structure in which a seed layer 21 for a plating process and a photoresist layer 22 were formed on the structure of
i) is a schematic view showing a cross-sectional structure in which a copper interconnection conductive layer 23 was formed on the structure shown in
j) is a schematic view showing a cross-sectional structure in which, after the photoresist 22 was removed from the structure shown in
According to a method of manufacturing a substrate including a functional element in this example, an interconnection layer and a metal pillar are preformed on a base substrate. If the base substrate is a functional element, the metal pillar is not provided directly on an electrode pad and is provided at a different position connected to the electrode pad by using a method of redistributing a functional element in this example. A functional element is mounted on the base substrate in a state in which a circuit element surface faces upward. The functional element and the metal pillar on the base substrate are embedded in an insulating resin layer. At that time, patterning is conducted so that the resin does not enter into a location of the functional element when a photosensitive resin or a printing method is used. Next, an insulating resin layer is supplied onto the functional element. At that time, since there has been no resin on the functional element, the film thickness of the resin can be controlled flexibly. The resin on the electrode pad of the functional element is removed by exposure and development or the like in a case where the resin is photosensitive or by dry etching or a laser in a case where the resin is non-photosensitive. Thus, a via hole is formed.
Then a sacrificial layer resin is supplied into the via hole. The top of the insulating resin and the top of the metal pillar are exposed by grinding or polishing. At that time, since there is resin on the electrode pad of the functional element, it is possible to prevent breakage of a brittle material such as a low-k material in the functional element due to transmission of stress. Furthermore, it is also possible to prevent grinding wastes from entering into the via hole. Moreover, a surface of the resin can be flattened. The sacrificial layer within the via hole is removed. A plating seed layer is formed, and a pattern of a plating resist is formed. Then electrolytic plating is conducted. A fine interconnection pattern can be formed on a flat surface of the resin around the via hole. The resist is removed, and the seed layer is etched. Thus, it is possible to form an interconnection conductive layer on the insulating resin that interconnects the exposed electrode pad of the functional element, the metal pillar, and the interconnection layer of the base substrate.
According to this example, shearing stress produced in a flattening process is relaxed by the sacrificial layer. Therefore, it is possible to form a fine interconnection conductive layer that can prevent breakage of the interior of the functional element, has excellent reliability and a high yield, and can achieve a high level of flatness.
A third example of the present invention will be described in detail with reference to the drawings. The details of the third example will specifically be described with reference to
a) shows a structure of an internal interconnection layer 32 of a functional element 31 and electrode pads 33 of Al that were provided on the uppermost layer of the internal interconnection layer 32 in a case where an LSI was used as the functional element 31. In FIG. 3(b), sacrificial layer pillars 34 having a height of 20 μm to 30 μm were formed on part of the electrode pads 33 with BCB made by the Dow Chemical Company. The sacrificial layer pillars 34 were formed on the electrode pads 33 by exposure and development. In
In a subsequent process of
Next, as shown in
After the electrolytic plating process, the photoresist 38 was removed with a solvent, and the seed layer 37 of Ti and Cu was etched with acid or alkali solution. Thus, the cross-sectional structure of
According to a method of redistributing a functional element in this example, an insulating resin layer is provided on a functional element wafer such as an LSI. A sacrificial layer pillar of resin is formed on an electrode pad by a photosensitive process or a laser. Then an insulating resin is supplied. The top of the sacrificial layer pillar is exposed by grinding or polishing. At that time, since resin is present on the electrode pad, it is possible to prevent separation produced between the insulating resin and a Cu pillar or between the insulating resin and a gold projecting electrode or breakage of a low-k material, which would be caused by transmission of shearing stress when a conventional pillar or a conventional gold projecting electrode is used. Simultaneously, it is possible to prevent grinding wastes from entering into the via hole. Furthermore, a surface of the insulating resin layer is flattened. Then the sacrificial layer resin within the via hole is removed by a solvent, heat, UV radiation, dry etching, or the like. A plating seed layer is formed, and a plating resist pattern is formed. Then electrolytic plating is conducted. At that time, a fine interconnection pattern can be formed on a flat surface of the resin around the via hole. The resist is removed, and the seed layer is etched. Thus, a redistribution layer is formed from the electrode pad. It is possible to form a conductive interconnection at a high density with excellent reliability.
A fourth example of the present invention will be described in detail with reference to the drawings.
a) is a view showing a structure in which, after a copper interconnection layer 42 was formed on a base substrate 41 with a thickness of 1 μm to 5 μm, Cu metal pillars 43 were formed on the interconnection layer 42 with a height of 10 μm to 50 μm. An 8-inch wafer or a 12-inch wafer of Si having a SiO2 layer formed between the interconnection layer 42 and the wafer was used as the base substrate. In a case where transistors are also formed inside of the base substrate, a design in which Cu pillars 43 are formed right above the electrode pads via the interconnection layer 42 is avoided such that damage of the base substrate can be prevented in a subsequent grinding process.
Subsequently, a functional element 45 having a thickness of 8 μm to 20 μm was mounted on a predetermined location of the interconnection layer 42, at which an alignment mark had been formed on the structure of
At that time, sacrificial layer pillars 47 preformed on electrode pads 46 of the functional element 45 faced upward. The adhesive layer 44 was supplied onto the base substrate 41 by a spin coating method. BCB made by the Dow Chemical Company for removing resin at locations other than locations requiring an adhesive by exposure and development or the LE series made by Lintec Corporation with a thickness of 15 μm to 20 μm that had been laminated on a rear face of the functional element 45 being mounted was used for the adhesive layer 14. The thickness and material of the adhesive were selected depending upon the thickness of the functional element and the thickness of the Cu pillars.
c) is a view showing a cross-sectional structure obtained by supplying an insulating layer 48 onto the structure of
If the resin has a low viscosity and the functional element has a thickness of 10 μm or larger, the structure of
d) is a schematic view showing a cross-sectional structure in which an insulating layer 49 was further supplied onto an upper surface of the structure of
e) is a schematic view showing a cross-sectional structure in which the tops of the sacrificial layer pillars 47 on the electrode pads 46 of the functional element 45 were exposed by polishing or grinding the structure shown in
f) is a schematic cross-sectional view showing that the sacrificial layer pillars 47 on the electrode pads 46 of the functional element 45 were removed by wet etching with a solvent or the like in the structure of
In a method of redistributing a functional element according to the present invention, there is illustrated an example in which the processes of
According to this example, shearing stress produced in a flattening process is relaxed by the sacrificial layer pillars. Therefore, it is possible to form a fine interconnection conductive layer that can prevent breakage of the interior of the functional element, has excellent reliability and a high yield, and can achieve a high level of flatness.
According to a method of redistributing a functional element of the present invention, an insulating resin layer is supplied onto a functional element wafer such as an LSI. The resin on an electrode pad is removed by a dry etching process, a photosensitive process, or a laser, thereby forming a via hole. Subsequently, the interior of the via hole is filled with a sacrificial layer by a spin coating method, a printing method, or a laminating method. Then the top of the insulating resin is exposed by grinding or polishing. At that time, since resin is present on the electrode pad, it is possible to prevent separation produced between the insulating resin and a Cu pillar or between the insulating resin and a gold projecting electrode or breakage of a low-k material, which would be caused by transmission of shearing stress when a conventional pillar or a conventional gold projecting electrode is used. Simultaneously, it is possible to prevent grinding wastes from entering into the via hole. Furthermore, a surface of the insulating resin layer is flattened. Then the sacrificial layer resin within the via hole is removed by a solvent, heat, or UV radiation. A plating seed layer is formed, and a plating resist pattern is formed. Then electrolytic plating is conducted. At that time, a fine interconnection pattern can be formed on a flat surface of the resin around the via hole. The resist is removed, and the seed layer is etched. Thus, a redistribution layer is formed from the electrode pad.
According to a method of manufacturing a substrate including a functional element of the present invention, an interconnection and a metal pillar are preformed on a base substrate. If the base substrate is a functional element, the metal pillar is not provided directly on an electrode pad and is provided at a different position connected to the electrode pad by using a method of redistributing a functional element in this example. A functional element is mounted on the base substrate in a state in which a circuit element surface faces upward. The functional element and the metal pillar on the base substrate are embedded in an insulating resin. At that time, patterning is conducted so that the resin does not enter into a location of the functional element when a photosensitive resin or a printing method is used. Next, an insulating resin is supplied onto the functional element. At that time, since there has been no resin on the functional element, the film thickness of the resin can be controlled flexibly. The resin on the electrode pad of the functional element is removed by exposure and development or the like in a case where the resin is photosensitive or by dry etching or a laser in a case where the resin is non-photosensitive. Thus, a via hole is formed. Then a sacrificial layer resin is supplied into the via hole. The top of the insulating resin and the top of the metal pillar are exposed by grinding or polishing.
At that time, since there is resin on the electrode pad of the functional element, it is possible to prevent breakage of a brittle material such as a low-k material in the functional element due to transmission of stress. Furthermore, it is also possible to prevent grinding wastes from entering into the via hole. Moreover, a surface of the resin can be flattened. The sacrificial layer within the via hole is removed. A plating seed layer is formed, and a pattern of a plating resist is formed. Then electrolytic plating is conducted. A fine interconnection pattern can be formed on a flat surface of the resin around the via hole. The resist is removed, and the seed layer is etched. Thus, it is possible to form an interconnection conductive layer on the insulating resin that connects the electrode pad of the functional element and the base substrate to the exposed metal pillar.
According to a method of redistributing a functional element of the present invention, an insulating resin layer is provided on a functional element wafer such as an LSI. A sacrificial layer pillar of resin is formed on an electrode pad by a photosensitive process or a laser. Then an insulating resin is supplied. The top of the sacrificial layer pillar is exposed by grinding or polishing. At that time, since resin is present on the electrode pad, it is possible to prevent separation produced between the insulating resin and a Cu pillar or between the insulating resin and a gold projecting electrode or breakage of a low-k material, which would be caused by transmission of shearing stress when a conventional pillar or a conventional gold projecting electrode is used. Simultaneously, it is possible to prevent grinding wastes from entering into the via hole. Furthermore, a surface of the insulating resin layer is flattened. Then the sacrificial layer resin within the via hole is removed by a solvent, heat, UV radiation, dry etching, or the like. A plating seed layer is formed, and a plating resist pattern is formed. Then electrolytic plating is conducted. At that time, a fine interconnection pattern can be formed on a flat surface of the resin around the via hole. The resist is removed, and the seed layer is etched. Thus, a redistribution layer is formed from the electrode pad. It is possible to form a conductive interconnection at a high density with excellent reliability.
Although the preferred embodiments of the present invention have been described above, the present invention is not limited to those embodiments. It should be understood that various changes and modifications may be made therein without departing from the scope of the present invention.
This application is based upon and claims the benefit of priority from Japanese patent application No. 2010-133785, filed on Jun. 11, 2010, the disclosure of which is incorporated herein in its entirety by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-133785 | Jun 2010 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2011/063856 | 6/10/2011 | WO | 00 | 5/24/2013 |
