SEMICONDUCTOR DEVICE AND MANUFACTURING THE SAME

Abstract

Disclosed is a semiconductor device which makes it easy to design a wiring pattern for a wiring substrate on which the semiconductor device is to be mounted. In manufacturing plural semiconductor devices for providing different amounts of output current, arrangements and numbers of leads to which semiconductor chips for power transistors of the semiconductor devices are to be electrically connected are changed according to output current requirements for the semiconductor devices, whereas arrangements and numbers of leads to which semiconductor chips for control circuits of the semiconductor devices are to be electrically connected are fixed to be common to the semiconductor devices. In this way, the probability of malfunction of control circuits (PWM circuits) of the semiconductor devices can be reduced, so that a semiconductor device which makes it easy to design a wiring pattern for a wiring substrate on which the semiconductor device is to be mounted can be provided.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram explanatory of a network power supply system including semiconductor devices according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example POL power supply including a semiconductor device shown in FIG. 1.

FIG. 3 shows a basic operation waveform of the POL power supply shown in FIG. 2.

FIG. 4 is an overall plan view of the top side of the semiconductor device making up the POL power supply shown in FIG. 2.

FIG. 5 is an overall plan view of the bottom side of the semiconductor device shown in FIG. 4.

FIG. 6 is a cross-sectional view taken along line X1--X1 in FIG. 4.

FIG. 7 is a side view of the semiconductor device shown in FIG. 4.

FIGS. 8( a) to 8(c) are plan views showing an example lineup of semiconductor devices based on the one shown in FIG. 4.

FIG. 9 is a plan view of essential parts of an electronic device including plural semiconductor devices to provide different amounts of output current.

FIG. 10 is a side view showing the electronic device shown in FIG. 9 as seen from the bottom side of FIG. 9.

FIG. 11 is an overall plan view of the principal surface of a semiconductor chip on which a high-side power transistor for the semiconductor device shown in FIG. 4 is formed.

FIG. 12 is an overall plan view of the principal surface of the semiconductor chip, showing a wiring layer under the layer shown in FIG. 11.

FIG. 13 is a cross-sectional view taken along line Y1-Y1 in FIGS. 11 and 12.

FIG. 14 is an enlarged cross-sectional view of a unit transistor cell of the high-side power transistor on the semiconductor chip shown in FIG. 11.

FIG. 15 is a flowchart showing a process for manufacturing the semiconductor device shown in FIG. 4.

FIG. 16 is an enlarged plan view of a unit device area of a lead frame for a semiconductor device for a relatively small output current.

FIG. 17 is an enlarged plan view of a unit device area of a lead frame for a semiconductor device for a relatively large output current.

FIG. 18 is an enlarged plan view of a unit device area, mounted with semiconductor chips, of a lead frame for a semiconductor device for a relatively small output current.

FIG. 19 is an enlarged plan view of a unit device area, mounted with semiconductor chips, of a lead frame for a semiconductor device for a relatively large output current.

FIG. 20 is an enlarged plan view of a unit device area, having been wire-bonded, of a lead frame for a semiconductor device for a relatively small output current.

FIG. 21 is an enlarged plan view of a unit device area, having been wire-bonded, of a lead frame for a semiconductor device for a relatively large output current.

FIG. 22 is an overall top plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 23 is a cross-sectional view taken along line X2-X2 in FIG. 22.

FIGS. 24( a) to 24(c) are plan views showing-an example lineup of semiconductor devices based on the one shown in FIG. 22.

FIG. 25 is a plan view of a semiconductor device, the semiconductor device having come through a wire bonding process.

FIG. 26 is a cross-sectional view taken along line X3-X3 in FIG. 25.

FIG. 27 is an overall plan view of the semiconductor device shown in FIG. 25, the semiconductor device having come through a cutting process.

FIG. 28 is a cross-sectional view taken along line X3-X3 in FIG. 27.

FIG. 29 is an overall plan view of a semiconductor device according to a third embodiment of the present invention, the semiconductor device having come through a cutting process.

FIG. 30 is a cross-sectional view taken along line X3-X3 in FIG. 29.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing first and second wiring substrates, each having first and second principal surfaces provided on opposite sides across a thickness thereof;(b) mounting a semiconductor chip for a first power transistor and a semiconductor chip for a first control circuit over the first principal surface of the first wiring substrate;(c) mounting a semiconductor chip for a second power transistor and a semiconductor chip for a second control circuit over the first principal surface of the second wiring substrate;(d) forming a first sealing body for sealing the semiconductor chip for the first power transistor and the semiconductor chip for the first control circuit; and(e) forming a second sealing body for sealing the semiconductor chip for the second power transistor and the semiconductor chip for the second control circuit,wherein an arrangement of external terminals, to be electrically connected to the semiconductor chip for the first control circuit, of the first wiring substrate and an arrangement of external terminals, to be electrically connected to the semiconductor chip for the second control circuit, of the second wiring substrate are identical, andwherein an arrangement of external terminals, to be electrically connected to the semiconductor chip for the first power transistor, of the first wiring substrate and an arrangement of external terminals, to be electrically connected to the semiconductor chip for the second power transistor, of the second wiring substrate are not identical.

2. The method of manufacturing a semiconductor device according to claim 1, wherein each of the first and second sealing bodies has first and second principal surfaces provided on opposite sides across a thickness thereof,wherein the first and second principal surfaces of the first and second sealing bodies are quadrilateral,wherein each of the first and second principal surfaces of the first and second sealing bodies has first and second sides, the first sides extending in a direction intersecting a direction in which the second sides extend,wherein the first sides of the first and second sealing bodies have an equal length, andwherein the second sides of the first sealing body are shorter than the second sides of the second sealing body.

3. The method of manufacturing a semiconductor device according to claim 2, wherein the first sides of the second sealing body are shorter than the second sides of the second sealing body.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip for the first power transistor and the semiconductor chip for the first control circuit are arranged such that longitudinal directions of the semiconductor chips intersect each other, andwherein the semiconductor chip for the second power transistor and the semiconductor chip for the second control circuit are arranged such that longitudinal directions of the semiconductor chips intersect each other.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip for the second power transistor is arranged such that the longitudinal direction thereof is along a longitudinal direction of the second sealing body.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip for the first control circuit and the semiconductor chip for the second control circuit have an equal area.

7. The method of manufacturing a semiconductor device according to claim 1, wherein each of the semiconductor chips for the first and second control circuits has a circuit which generates a pulse width modulation signal.

8. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a wiring substrate having first and second principal surfaces provided on opposite sides across a thickness thereof; and(b) mounting a semiconductor chip for a power transistor and a semiconductor chip for a control circuit over the first principal surface of the wiring substrate,wherein the step (a) includes fixing an arrangement of external terminals, out of external terminals arranged over the second principal surface of the wiring substrate, to be electrically connected to the semiconductor chip for the control circuit and changing an arrangement of external terminals, out of the external terminals arranged over the second principal surface of the wiring substrate, to be electrically connected to the semiconductor chip for the power transistor.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor chip for the power transistor is arranged such that a longitudinal direction thereof intersects a longitudinal direction of the semiconductor chip for the control circuit, andwherein the method includes changing lengths of sides of the semiconductor chip for the power transistor.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the method includes changing the lengths of sides, out of the sides of the semiconductor chip for the power transistor, which extend in a direction intersecting the longitudinal direction of the semiconductor chip for the control circuit.

11. A semiconductor device, comprising: a wiring substrate having first and second principal surfaces provided on opposite sides across a thickness thereof;a semiconductor chip for a power transistor and a semiconductor chip for a control circuit which are mounted over the first principal surface of the wiring substrate; anda sealing body which seals the semiconductor chip for the power transistor and the semiconductor chip for the control circuit,wherein the sealing body has first and second principal surfaces provided on opposite sides across a thickness thereof,wherein the first and second principal surfaces of the sealing body are quadrilateral,wherein a plurality of first external terminals electrically connected to the semiconductor chip for the control circuit and a plurality of second external terminals electrically connected to the semiconductor chip for the power transistor are arranged along four sides of the second principal surface of the sealing body, andwherein the semiconductor chip for the power transistor and the semiconductor chip for the control circuit are arranged such that the longitudinal directions of the semiconductor chips intersect each other.

12. The semiconductor device according to claim 11, wherein the semiconductor chip for the control circuit has a circuit which generates a pulse width modulation signal.

13. The semiconductor device according to claim 11, wherein the semiconductor device has a QFN structure.

14. The semiconductor device according to claim 11, wherein the semiconductor device has a QFP structure.

15. A semiconductor device, comprising a first semiconductor device and a second semiconductor device, wherein the first semiconductor device includes:a fist wiring substrate having first and second principal surfaces provided on opposite sides across a thickness thereof;a semiconductor chip for a first power transistor and a semiconductor chip for a first control circuit which are mounted over the first principal surface of the first wiring substrate; anda first sealing body which seals the semiconductor chip for the first power transistor and the semiconductor chip for the first control circuit,wherein the second semiconductor device includes: a second wiring substrate having first and second principal surfaces provided on opposite sides across a thickness thereof;a semiconductor chip for a second power transistor and a semiconductor chip for a second control circuit which are mounted over the first principal surface of the second wiring substrate; anda second sealing body which seals the semiconductor chip for the second power transistor and the semiconductor chip for the second control circuit,wherein an arrangement of external terminals, to be electrically connected to the semiconductor chip for the first control circuit, of the first wiring substrate and an arrangement of external terminals, to be electrically connected to the semiconductor chip for the second control circuit, of the second wiring substrate are identical, andwherein an arrangement of external terminals, to be electrically connected to the semiconductor chip for the first power transistor, over the second principal surface of the first wiring substrate and an arrangement of external terminals, to be electrically connected to the semiconductor chip for the second power transistor, over the second principal surface of the second wiring substrate are not identical.

16. The semiconductor device according to claim 15, wherein each of the first and second sealing bodies has first and second principal surfaces provided on opposite sides across a thickness thereof,wherein the first and second principal surfaces of the first and second sealing bodies are quadrilateral,wherein each of the first and second principal surfaces of the first and second sealing bodies has first and second sides, the first sides extending in a direction intersecting a direction in which the second sides extend,wherein the first sides of the first and second sealing bodies have an equal length, andwherein the second sides of the first sealing body are shorter than the second sides of the second sealing body.

17. A semiconductor device, comprising: a wiring substrate having first and second principal surfaces provided on opposite sides across a thickness thereof;a plurality of semiconductor chips for power transistors mounted over the first principal surface of the wiring substrate; anda semiconductor chip for a control circuit mounted over the first principal surface of the wiring substrate,wherein the wiring substrate includes a plurality of external terminals electrically connected to the semiconductor chip for the control circuit and a plurality of external terminals electrically connected to the plurality of semiconductor chips for the power transistors, andwherein the power transistors formed over the plurality of semiconductor chips for the power transistors are electrically connected in parallel.

18. The semiconductor device according to claim 17, wherein each of the plurality of semiconductor chips for the power transistors includes a low-side power transistor for a DC/DC converter, andwherein in addition to the plurality of semiconductor chips including the low-side power transistors, a semiconductor chip including a high-side power transistor for the DC/DC converter is mounted over the first principal surface of the wiring substrate.

19. The semiconductor device according to claim 17, wherein a sum of long-side lengths of the plurality of semiconductor chips including the low-side power transistors is larger than a long-side length of the semiconductor chip including the high-side power transistor.