Patent Grant
8759982
The present invention relates to microelectronic packages or assemblies and methods of making such assemblies, and to components useful in such assemblies.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is mounted in a package which, in turn, is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face. In “flip chip” designs, the front face of the chip confronts the face of a package substrate, i.e., chip carrier and the contacts on the chip are bonded directly to contacts of the chip carrier by solder balls or other connecting elements. In turn, the chip carrier can be bonded to a circuit panel through terminals overlying the front face of the chip. The “flip chip” design provides a relatively compact arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip's front face, such as disclosed, for example, in certain embodiments of commonly-assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,679,977, the disclosures of which are incorporated herein by reference.
Certain innovative mounting techniques offer compactness approaching or equal to that of conventional flip-chip bonding. Packages which can accommodate a single chip in an area of the circuit panel equal to or slightly larger than the area of the chip itself are commonly referred to as “chip-sized packages.”
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The interconnections should be short and should have low impedance to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines. For example, structures which provide numerous short, low-impedance interconnects between complex chips can increase the bandwidth of the search engine and reduce its power consumption.
Packages and assemblies containing multiple chips are common for packaging chips that contain memory storage arrays, particularly for dynamic random access memory chips (DRAMs) and flash memory chips. Each package has many electrical connections for carrying signals, power and ground between terminals, i.e., external connection points of the package, and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extending in both horizontal and vertical directions relative to the surface of the chip.
The transmission of signals within packages to chips of multi-chip packages poses particular challenges, especially for signals common to two or more chips in the package such as clock signals, and address and strobe signals for memory chips. Within such multi-chip packages, the lengths of the connection paths between the terminals of the package and the chips can vary. The different path lengths can cause the signals to take longer or shorter times to travel between the terminals and each chip.
Travel time of a signal from one point to another is called “propagation delay” and is a function of the conductor length, the conductor's structure, i.e., width, and other dielectric or conductive structure in close proximity therewith.
Differences in the times at which a particular signal arrives at different locations is called “skew”. Differences in the times at which two different signals reach a particular location can also be called “skew”. The skew in the arrival times of a particular signal at two or more locations is a result of both propagation delay and the times at which the particular signal starts to travel towards the locations. Skew may or may not impact circuit performance. Skew often has little impact on performance when all signals in a synchronous group of signals are skewed together, in which case all signals needed for operation arrive together when needed. However, this is not the case when different signals of a group of synchronous signals needed for operation arrive at different times. In this case the skew impacts performance because the operation cannot be performed unless all needed signals have arrived.
The problem with synchronous signals from the package arriving at the contacts of a chip at different times is that this limits the speed or frequency at which the chip can transmit or receive the signals. To function properly, all synchronous signals required for an operation need to have arrived before the operation can be performed. A consequence of synchronous signals arriving at different times is that the frequency used to clock the signals into the chip may have to decrease.
In light of the background described above, further improvements can be made to multi-chip packages and assemblies to address skew.
A microelectronic package according to an aspect of the invention includes packaging structure having a plurality of terminals disposed at a face thereof, the terminals being configured for connecting the microelectronic package to at least one component external to the package. First and second microelectronic elements can be affixed with the packaging structure. The package includes connections electrically coupling the terminals of the package with the first and second microelectronic elements. The connections can include groups of connections for carrying respective signals, each group including two or more connections, e.g., a first connection extending from a respective terminal of the package to a corresponding contact on the first microelectronic element and a second connection extending from the respective terminal to a corresponding contact on the second microelectronic element. The first and second connections can be configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.
In accordance with a particular aspect of the invention, a difference between the total electrical lengths of the connections in a respective group of the connections can be not greater than 10 per cent, even when distances along straight lines between the terminal and the respective contacts coupled by such group of connections varies by greater than 10 per cent.
In accordance with an aspect of the invention, the matched delay may result at least partly from differences in a spacing of conductors in the electrical connections relative to other conductive structure of the substrate.
In accordance with an aspect of the invention, a microelectronic package may further include a circuit panel having circuit contacts, wherein the terminals of the package are electrically connected to the circuit contacts.
In accordance with a particular aspect of the invention, at least one of the signals may be a clock signal or a command signal.
In accordance with a particular aspect of the invention, the signals may include a plurality of address signals and a sampling signal used to sample the address signals.
In accordance with a particular aspect of the invention, the signals may further include a command strobe signal.
In accordance with a particular aspect of the invention, the same duration of the propagation delay of the respective signal on the first and second connections within each group may be within a tolerance of ten per cent of the cycle time of that signal.
In accordance with a particular aspect of the invention, a third microelectronic element may be affixed with the packaging structure, wherein at least one of the groups of connections includes a third connection electrically coupling the respective terminal to a corresponding contact of the third microelectronic element for carrying the respective signal thereto, wherein the signal carried by the first, second and third connections is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto. In a particular example, a fourth microelectronic element may also affixed with the packaging structure, wherein at least one of the groups of connections includes a fourth connection electrically coupling the respective terminal to a corresponding contact of the fourth microelectronic element for carrying the respective signal thereto, wherein the signal carried by the first, second, third and fourth connections is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.
In accordance with a particular aspect of the invention, the packaging structure may have edges bounding the face, the face having a central region occupying a central portion thereof, and a second region occupying a portion of the face between the central portion and at least one of the edges. The terminals may include first terminals exposed at the central region and second terminals exposed at the second region, and the groups of connections couple the first terminals with the corresponding contacts. In such case, in a particular example, the microelectronic package may include further connections electrically coupling the second terminals with contacts of the microelectronic elements.
In accordance with a particular aspect of the invention, the packaging structure may include a substrate having first and second opposed surfaces, the first surface facing away from the microelectronic elements and the second surface facing towards the microelectronic elements, at least first and second apertures extending between the first and second surfaces. In a particular example, the apertures may have long dimensions with lengths which extend along axes parallel to one another. The central region may be bounded at least partly by the first and second apertures, and the connections can include leads which have portions aligned with at least one of the first or second apertures. In accordance with a particular aspect of the invention, the leads which have portions aligned with at least one of the apertures can include wire bonds. In a particular example thereof, the microelectronic package may further include third and fourth microelectronic elements each affixed with the packaging structure, wherein at least one of the groups of connections includes third and fourth connections electrically coupling the respective terminal to corresponding contacts of the third and fourth microelectronic elements for carrying the respective signal thereto, wherein the signal carried by the first, second, third and fourth connections is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto. In accordance with a particular aspect, the parallel axes can be first parallel axes, and the substrate can further include third and fourth apertures which extend between the first and second surfaces. The third and fourth apertures can have long dimensions having lengths extending along second axes parallel to one another, the second parallel axes being transverse to the first parallel axes, wherein the central region is bounded at least partly by the third and fourth apertures, and the connections include leads having portions aligned with at least one of the third or fourth apertures.
In accordance with a particular aspect of the invention, each of the first, second, third and fourth microelectronic elements is configured to provide predominantly a memory storage function.
In accordance with a particular example, third and fourth microelectronic elements can be affixed with the packaging structure, wherein at least one of the groups of connections includes third and fourth connections electrically coupling the respective terminal to corresponding contacts of the third and fourth microelectronic elements for carrying the respective signal thereto. The first, second, third and fourth connections can be configured such that the signal carried by the first, second, third and fourth connections is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto. In a particular example, the central region of the face can be bounded by first parallel axes and second parallel axes transverse to the first parallel axes. Each first axis may bisect an area of one of the first and second microelectronic elements, respectively, and may extend in a direction parallel to first and second opposed edges of each of the first and second microelectronic elements. Each second axis may bisect an area of one of the third and fourth microelectronic elements, respectively, and may extend in a direction parallel to first and second opposed edges of each of the third and fourth microelectronic elements.
In accordance with a particular aspect of the invention, the packaging structure may include a substrate having contacts at a surface facing the microelectronic elements, the contacts of the microelectronic elements facing the substrate contacts and joined thereto. In accordance with a particular example, each of the first parallel axes may intersects exactly one of the third or fourth microelectronic elements, and each of the second parallel axes may intersect exactly one of the first or second microelectronic elements.
In accordance with a particular aspect of the invention, the microelectronic package may further include a circuit panel having panel contacts adjacent and electrically connected to the terminals, the circuit panel having conductive elements thereon which provide delay matching, such that signals carried by each group of connections to the microelectronic elements are subject to delay of the same duration through the packaging structure and the circuit panel.
In accordance with a particular aspect of the invention, the first and second microelectronic elements can be spaced apart from one another in a direction parallel to the face of the packaging structure.
In accordance with a particular aspect of the invention, the packaging structure may include a substrate having at least one aperture extending through the substrate, and the second microelectronic element may partially overlie the first microelectronic element such that contacts of the second microelectronic element are disposed beyond an edge of the first microelectronic element, wherein the connections to the corresponding contacts of the second microelectronic element include leads having portions aligned with the at least one aperture.
In accordance with a particular aspect of the invention, the leads can include wire bonds which extend through the at least one aperture.
In accordance with a particular aspect of the invention, the at least one aperture may include first and second bond windows, and the connections can include first leads coupled to the first microelectronic element having portions aligned with the first bond window, and second leads coupled to the second microelectronic element having portions aligned with the second bond window.
In accordance with a particular aspect of the invention, at least some of the terminals with which the first and second leads are coupled can be disposed between the first and second bond windows.
In accordance with a particular aspect of the invention, the first microelectronic element may have contacts at a front face thereof and a rear face opposed to the front face. The rear face may be mounted to the packaging structure, and the leads may include wire bonds connected between the contacts and the packaging structure.
In accordance with a particular aspect of the invention, at least one of the first or second microelectronic elements may include a memory storage array and at least one of the first or second microelectronic elements may include a microcontroller.
In accordance with a particular aspect of the invention, the packaging structure may include a dielectric layer formed on the contact-bearing surfaces of the first and second microelectronic elements, traces extending in a direction parallel to the dielectric layer, and metalized vias extending at least partly through a thickness of the dielectric layer and electrically coupled with the contacts of the first and second microelectronic elements, wherein the terminals are electrically connected to the contacts by the traces and the vias.
A method of making a microelectronic package according to an aspect of the invention can include forming electrical connections coupling first and second microelectronic elements with packaging structure having a plurality of terminals disposed at a face thereof, the terminals being configured for connecting the microelectronic package to at least one component external to the package. The connections can include groups of connections for carrying respective signals, each group including two or more connections, e.g., a first connection extending from a respective terminal of the package to a corresponding contact on the first microelectronic element and a second connection extending from the respective terminal to a corresponding contact on the second microelectronic element. The first and second connections can be configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.
In accordance with a particular aspect of the invention, the packaging structure may have edges bounding the face, and the face may have a central region occupying a central portion thereof, and a second region occupying a portion of the face between the central portion and at least one of the edges. The terminals can include first terminals exposed at the central region and second terminals exposed at the second region. The groups of connections may couple the first terminals with the corresponding contacts, and the microelectronic package can include further connections electrically coupling the second terminals with contacts of the microelectronic elements.
In accordance with a particular aspect of the invention, the packaging structure can include a substrate having at least one aperture extending through the substrate, and the second microelectronic element may partially overlie the first microelectronic element. In such way, contacts of the second microelectronic element can be disposed beyond an edge of the first microelectronic element. Connections to the corresponding contacts of the second microelectronic element may include leads having portions aligned with the at least one aperture.
Embodiments of the invention herein provide packages which have more than one semiconductor chip, i.e., a microelectronic element therein. A multiple chip package can reduce the amount of area or space required to connect the chips therein to a circuit panel, e.g., printed wiring board to which the package may be electrically and mechanically connected through an array of terminals, such as a ball grid array, land grid array or pin grid array, among others. Such connection space is particularly limited in small or portable computing devices, e.g., handheld devices such as “smartphones” or tablets which typically combine the function of personal computers with wireless connectivity to the broader world. Multi-chip packages can be particularly useful for making large amounts of relatively inexpensive memory available to a system, such as advanced high performance dynamic random access memory (“DRAM”) chips, e.g., in DDR3 type DRAM chips and its follow-ons.
The amount of area of the circuit panel needed to connect the multi-chip package thereto can be reduced by providing common terminals on the package through which at least some signals travel on their way to or from two or more chips within the package. However, doing so in a way that supports high performance operation presents challenges. To avoid undesirable effects such as noise and propagation delays within the package, the traces, vias, and other conductors which electrically connect the terminals at the exterior of the package with the chips therein must not be too long or too narrow in order to avoid excessive inductance and stub length, and must not have excessive capacitance. Heat dissipation also presents a challenge for advanced chips, such that it is desirable for at least one of the large flat surfaces of each chip to be coupled to a heat spreader or be exposed to or in thermal communication with a flow or air within an installed system. The packages described below can help to further these goals.
Embodiments of the invention herein provide ways of de-skewing signals carried within microelectronic packages that have at least two microelectronic elements, wherein each of a plurality of microelectronic elements in the package transmits or receives some of the same signals through a set of common terminals of the package. Thus, corresponding contacts of multiple chips within the package can be electrically connected with a single common terminal of the package which is configured for connection with a component external to the package, e.g., a circuit panel such as printed circuit board, external microelectronic element or other component.
The structures and processes herein help to achieve a de-skewed timing of a signal from a common package terminal to contacts on more than one chip through one or more of the following: placement of at least some common terminals of the package used for carrying time-varying signals in a region of the package between at least two of the chips; and design of traces or other conductors of the package such that the signal propagation delay between each common terminal and the corresponding contacts of each chip connected thereto is the same, i.e., within a limited tolerance.
The package includes packaging structure, for example, an optional substrate 30 with terminals 36, e.g., conductive pads 36, lands or conductive posts thereon. In some cases, the substrate may consist essentially of a material having a low coefficient of thermal expansion (“CTE”), i.e., a CTE of less than 10 parts per million per degree Celsius (hereinafter, “ppm/° C.”), such as a semiconductor material e.g., silicon, or a dielectric material such as ceramic material or silicon dioxide, e.g., glass. Alternatively, the substrate may include a sheet-like dielectric element which can consist essentially of a polymeric material such as polyimide, epoxy, thermoplastic, thermoset plastic, or other suitable polymeric material or which includes or consists essentially of composite polymeric-inorganic material such as a glass reinforced structure of BT resin (bismaleimide triazine) or epoxy-glass, such as FR-4, among others. Electrical connections between the contacts 20 and terminals 36 can include optional leads, e.g., wire bonds 72, 74, or other possible structure in which at least portions of the leads are aligned with an aperture extending between surfaces 32, 34 of the substrate. For example, as seen in
The terminals 36 function as endpoints for the connection of the microelectronic package 10 with corresponding electrically conductive elements of an external component such as a circuit panel, e.g., printed wiring board, flexible circuit panel, socket, other microelectronic assembly or package, interposer, or passive component assembly, among others. In a particular example, the terminals of the package 10 may include joining elements 38, e.g., conductive masses such as solder balls, masses of conductive material, such as conductive paste, conductive matrix material, or conductive adhesive attached to the terminals.
As further seen in
In a particular embodiment as seen in
In a particular embodiment, the leads can include or be beam leads 73 which extend along a surface 34 of the substrate which faces the surface 16, 22 of the first or second microelectronic elements, or both microelectronic elements and extends beyond an edge of an aperture 33 or 39 to contacts 20 or contacts 26 or both. In another embodiment, beam leads 75 can extend along a surface 32 of the substrate at the face of the packaging structure. In one embodiment, beam leads 73 and 75 can exist in the same package. An encapsulant 82 may optionally cover at least a portion of the leads and extend into the apertures or gaps of the packaging structure.
As further seen in
The package may further include an adhesive 60 between the adjacent faces of the first and second microelectronic elements 12, 14, and an encapsulant 62 contacting edge surfaces 27, 29, 40, 42. The encapsulant may optionally cover, partially cover, or leave uncovered the rear surfaces 15, 24 of the microelectronic elements 12, 14. For example, in the package shown in
As depicted in the bottom plan view of the microelectronic package 10 in
In the embodiment of
Referring to
The package 110 may be a fan-out wafer-level package having a land grid array (“LGA”) or ball grid array (“BGA”) style connection arrangement of terminals thereon. The package 110 may have an encapsulant 62 extending beyond edges 27, 42 of the microelectronic elements 12, 14. The encapsulant 62 may be an overmold which has a surface 17 co-planar with or generally co-planar with a contact-bearing surface 16 of first microelectronic element 12. The dielectric layer 90 may overlie the encapsulant 62 and some of the terminals or traces can overlie the encapsulant 62.
Package 110 may be made according to techniques as described in one or more embodiments described in commonly owned U.S. application Ser. No. 12/953,994 filed Nov. 24, 2010, the disclosure of which is incorporated by reference herein. However, specific features, e.g., relative trace lengths, relative propagation delay between a terminal and corresponding contacts coupled thereto, and assignment and placement of package terminals for carrying particular signals are as described herein.
As further shown in
Referring to
However, even when signals are routed through common central terminals, the structure can be configured further to de-skew the signals which pass therethrough to and from each microelectronic element. Signal de-skewing can be provided by ensuring that the electrical connections between each common terminal and contacts on each microelectronic element connected thereto have matched delays such that the signal carried on each of the electrical connections is subject to propagation delay of the same duration between the respective common central terminal and the corresponding contacts on each of the first and second microelectronic elements.
One way that matched propagation delays can be achieved between a common terminal and each microelectronic element is to structure the traces and other conductive elements on each path or connection from the common terminal to the respective microelectronic element (e.g., as seen in
In addition, when the paths include wire bonds and traces, the length of the wire bond can be increased for the path which includes a shorter trace, or the length of the wire bond can be decreased for the path which includes a longer trace.
In another example, the degree of shielding which exists for a path in a package can be selectively reduced to reduce the delay on one path relative to another path, or can be selectively increased to increase the delay on a path relative to another path. For example, if the package includes a ground or power plane overlying conductors of the respective paths, a portion of such ground or power plane can be removed overlying one conductor such that a portion of the length of such conductor is unshielded, therefore reducing capacitance between such conductor and the ground or power plane. In this way, the reduced capacitance for the unshielded portion of the conductor has an effect of reducing the delay on such conductor.
In addition alternatively, an air gap can be created where appropriate to decrease the delay along a particular path, or the dielectric constant at a particular location of the substrate can be varied by allowing a particular dielectric material having a different dielectric constant, e.g., an encapsulant, solder mask, etc. to flow into location during fabrication.
As best seen in
The positions of a central region and a second or peripheral region of the substrate 830 of
Second terminals 136 typically are distributed throughout a peripheral region 872 of the substrate disposed beyond edges of the central region 870. The peripheral region can be disposed beyond apertures 853, 855, 857, 859, being bounded by edges 832, 834 of the substrate and edges of the apertures as illustratively shown at 862. Typically, a second terminal connects only to a single contact of a single microelectronic element, although exceptions of course exist. The need to arrange structure within the package to de-skew signals carried by the second terminals, i.e., to make propagation delays the same from second terminals to the contacts the same, is not critical. This is because conductive elements on a circuit panel or board to which the package is connected can be arranged to selectively provide de-skewing to individual ones of the second terminals where needed. However, it is possible for a second terminal to be electrically coupled to more than one contact of a microelectronic element 812, 814, 816 or 818 within the package, or to corresponding contacts on more than one of the microelectronic elements. In this case, the potential, e.g., power or ground, or the signal carried by such second terminal can be one which is less sensitive to differences in arrival times of the potential or signal, i.e., to “skew”, and therefore, no special arrangement may be needed on the package to compensate for the skew.
The arrangement of microelectronic elements 1012, 1014, 1016, 1018 on substrate 1030 defines a central region 1070 of the substrate having a boundary generally as shown by dashed line 1072, i.e., a rectangular area that is bounded by the apertures 1033, 1039, 1043, and 1049. Peripheral region 1074 lies outside of boundary 1072. The arrangement shown in
In variations of the embodiments described above it is possible for the contacts of microelectronic elements to not be disposed in central regions of the surfaces thereof. Rather, the contacts may be disposed in one or more rows adjacent an edge of such microelectronic element. In another variation, the contacts of a microelectronic element can be disposed adjacent two opposed edges of such microelectronic element. In yet another variation, the contacts of a microelectronic element can be disposed adjacent any two edges, or be disposed adjacent more than two edges of such microelectronic element. In such cases, locations of apertures in the substrate can be modified to correspond to such locations of the contacts disposed adjacent such edge or edges of the microelectronic element.
In one embodiment, the packaging structure may include a dielectric layer formed on surfaces of the microelectronic elements and conductive structure defining a redistribution layer thereon, such as described above relative to
In another embodiment, the packaging structure can include a substrate having substrate contacts on a surface of the substrate. Corresponding contacts of the microelectronic elements can be arranged such that the contacts face the substrate contacts and be joined thereto in a flip-chip configuration, such as with conductive masses, e.g., masses of a bond metal such as solder, tin, indium, eutectic composition or combination thereof or other joining material such as a conductive paste. In a particular embodiment, the joints between the contacts and the substrate contacts can include an electrically conductive matrix material such as described in commonly owned U.S. application Ser. No. 13/155,719 filed Jun. 8, 2011 and Ser. No. 13/158,797 filed Jun. 13, 2011, the disclosures of which are incorporated by reference herein. In a particular embodiment, the joints can have a similar structure or be formed in a manner as described therein.
In a particular embodiment, one or more of the microelectronic elements may include a semiconductor chip having bond pads disposed in one, two, or more parallel adjacent rows thereon. In a particular embodiment, all of the rows of contacts can be disposed in a central region of the surface of such chip. Such microelectronic element can have a conductive redistribution layer formed thereon. For example, such microelectronic element can include a redistribution layer having metallized vias 92 and traces 94 coupled to the contacts 20 of the microelectronic element and overlying the contact-bearing surface of microelectronic element 12, as seen in
In another variation, first, second, third and fourth microelectronic elements, e.g., semiconductor chips 1112, 1114, 1116, and 1118 having contacts, e.g., bond pads, thereon can be arranged as seen in
Contacts of microelectronic elements 1112, 1114, 1116, 1118 can be disposed in one or more rows within a central region of the microelectronic element, e.g., as described above relative to
In the embodiment depicted in
In variations of the above-described embodiments as illustrated in any of the foregoing figures, one or more microelectronic elements therein can each be configured to predominantly provide a memory storage array function, e.g., as flash memory, DRAM or other type of memory. Such “memory” microelectronic element or “memory chip” may have a greater number of active circuit elements, e.g., active semiconductor devices, which are configured to provide memory storage array function than any other function of the microelectronic element. Such one or more memory microelectronic elements can be arranged in a package together with another “logic” microelectronic element or “logic chip” which is configured to predominantly provide logic function. Such “logic” microelectronic element or chip may have a greater number of active circuit elements, e.g., active semiconductor devices, which are configured to provide logic function than any other function of the microelectronic element.
In a particular embodiment, the logic chip can be a programmable or processor element such as a microprocessor or other general purpose computing element. The logic chip can be a microcontroller element, graphics processor, floating point processor, co-processor, digital signal processor, etc. In a particular embodiment, the logic chip can predominantly perform hardware state machine functions, or otherwise be hard-coded to serve a particular function or purpose. Alternatively, the logic chip can be an application specific integrated circuit (“ASIC”) or field programmable gate array (“FPGA”) chip. In such variation, the package then may be a “system in a package” (“SIP”).
In another variation, a microelectronic element in the package can have both logic and memory function embedded therein, such as a programmable processor having one or more associated memory storage arrays embedded therewith in the same microelectronic element. Such microelectronic element is sometimes referred to as a “system-on-a-chip” (“SOC”), in that logic such as a processor is embedded together with other circuitry such as a memory storage array or circuitry for performing some other function, which may be a specialized function.
The structures discussed above can be utilized in construction of diverse electronic systems. For example, as shown in
Principles of the invention as described relative to any or all of the figures herein can be applied to the fabrication, i.e., a method of making a microelectronic package. Thus, a method of making a microelectronic package according to an embodiment of the invention can include forming electrical connections coupling first and second microelectronic elements with packaging structure having a plurality of terminals disposed at a face thereof such as seen in the figures as described above, the terminals being configured for connecting the microelectronic package to at least one component external to the package. The connections can include groups of connections for carrying respective signals, each group including a first connection extending from a respective terminal of the package to a corresponding contact on the first microelectronic element and a second connection extending from the respective terminal to a corresponding contact on the second microelectronic element, such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.
Methods of fabricating microelectronic packages embodying additional features or further enhancements as described above can be made in accordance with the disclosure herein.
Various features of the above-described embodiments of the invention can be combined in ways other than as specifically described above without departing from the scope or spirit of the invention. It is intended for the present disclosure to cover all such combinations and variations of embodiments of the invention described above.
Moreover, in any of the embodiments described in the foregoing, the one or more second semiconductor chips can be implemented in one or more of the following technologies: DRAM, NAND flash memory, RRAM (“resistive RAM” or “resistive random access memory”), phase-change memory (“PCM”), magnetoresistive random access memory, e.g. such as may embody tunnel junction devices, spin-torque RAM, or content addressable memory, among others.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
The present application is a continuation of U.S. patent application Ser. No. 13/306,068, filed Nov. 29, 2011, which application claims the benefit of the filing date of U.S. Provisional Application 61/506,889 filed Jul. 12, 2011, the disclosures of which are hereby incorporated herein by reference.
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| Number | Date | Country | |
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| 20130307138 A1 | Nov 2013 | US |
| Number | Date | Country | |
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| 61506889 | Jul 2011 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13306068 | Nov 2011 | US |
| Child | 13950912 | US |
