Patent Grant
10134711
The present invention relates to a semiconductor assembly and, more particularly, to a thermally enhanced semiconductor assembly with three dimensional integration in which a stacked semiconductor sub-assembly is wire bonded to and thermally conductible to a wiring board having a heat spreader integrated with dual wiring structures, and a method of making the same.
Market trends of multimedia devices demand for faster and slimmer designs. One of assembly approaches is to interconnect two devices with stacking configuration so that the routing distance between the two devices can be the shortest possible. As the stacked devices can talk directly to each other with reduced latency, the assembly's signal integrity and additional power saving capability are greatly improved. However, as semiconductor devices are susceptible to performance degradation at high operational temperatures, stacking chips without proper heat dissipation would worsen devices' thermal environment and may cause immediate failure during operation.
Additionally, U.S. Pat. Nos. 8,008,121, 8,519,537 and 8,558,395 disclose various assembly structures having an interposer disposed in between the face-to-face chips. Although there is no TSV in the stacked chips, the TSV in the interposer that serves for circuitry routing between chips induces complicated manufacturing processes, high yield loss and excessive cost.
For the reasons stated above, and for other reasons stated below, an urgent need exists to provide a three dimensional semiconductor assembly that can address high packaging density, better signal integrity and high thermal dissipation requirements.
The objective of the present invention is to provide a thermally enhanced semiconductor assembly in which a stacked semiconductor sub-assembly is electrically connected to a wiring board through a plurality of bonding wires and thermal conductible to a heat spreader provided in the wiring board. The heat spreader is disposed in a through opening of a wiring structure and mechanically supported by, electrically connected with, and thermally dissipated through another wiring structure, thereby improving mechanical, thermal and electrical performances of the assembly.
In accordance with the foregoing and other objectives, the present invention provides a thermally enhanced semiconductor assembly having a stacked semiconductor sub-assembly electrically connected to a wiring board through bonding wires. The stacked semiconductor sub-assembly includes a first device, a second device and a routing circuitry. The wiring board includes a heat spreader, a first wiring structure and a second wiring structure. In a preferred embodiment, the first device is thermally conductible to the heat spreader and spaced from and electrically connected to the second device through the routing circuitry; the routing circuitry provides primary fan-out routing and the shortest interconnection distance between the first device and the second device; the first wiring structure laterally surrounds peripheral edges of the heat spreader and the sub-assembly, and is electrically coupled to the routing circuitry by bonding wires to provide further fan-out routing; and the second wiring structure covers the first wiring structure and the heat spreader to provide mechanically support, and is thermally conductible to the heat spreader and electrically coupled to the first wiring structure.
Accordingly, the present invention provides a thermally enhanced semiconductor assembly with three dimensional integration, comprising: a stacked semiconductor sub-assembly that includes a first device, a second device and a routing circuitry, wherein the first device is electrically coupled to a first surface of the routing circuitry and the second device is electrically coupled to a second surface of the routing circuitry opposite to the first surface; a wiring board that includes a first wiring structure, a second wiring structure and a heat spreader, wherein (i) the first wiring structure has a first surface, an opposite second surface, and a through opening extending from the first surface and to the second surface, (ii) the heat spreader is disposed in the through opening and has a backside surface substantially coplanar with the first surface of the first wiring structure, (iii) the second wiring structure is disposed on the backside surface of the heat spreader and the first surface of the first wiring structure and electrically connected to the first wiring structure and thermally conductible to the heat spreader through metallized vias, and (iv) the stacked semiconductor sub-assembly is disposed in the through opening; and a plurality of bonding wires that electrically couple the routing circuitry to the wiring board.
Additionally, the present invention provides a method of making a thermally enhanced semiconductor assembly with three dimensional integration, comprising: providing a stacked semiconductor sub-assembly that includes a first device, a second device and a routing circuitry, wherein the first device is electrically coupled to a first surface of the routing circuitry and the second device is electrically coupled to a second surface of the routing circuitry opposite to the first surface; providing a wiring board that includes a first wiring structure, a second wiring structure and a heat spreader, wherein (i) the first wiring structure has a first surface, an opposite second surface, and a through opening extending from the first surface to the second surface, (ii) the heat spreader is disposed in the through opening and has a backside surface substantially coplanar with the first surface of the first wiring structure, and (iii) the second wiring structure is disposed on the backside surface of the heat spreader and the first surface of the first wiring structure and electrically connected to the first wiring structure and thermally conductible to the heat spreader through metallized vias; disposing the stacked semiconductor sub-assembly in the through opening of the first wiring structure and over the heat spreader; and providing a plurality of bonding wires that electrically couple the routing circuitry and the wiring board.
Unless specifically indicated or using the term “then” between steps, or steps necessarily occurring in a certain order, the sequence of the above-mentioned steps is not limited to that set forth above and may be changed or reordered according to desired design.
The semiconductor assembly and the method of making the same according to the present invention have numerous advantages. For instance, stacking and electrically coupling the first and second devices to both opposite sides of the routing circuitry can offer the shortest interconnect distance between the first and second devices. Inserting the sub-assembly into the through opening of the first wiring structure of the wiring board is particularly advantageous as the wiring board can provide mechanical housing for the sub-assembly, whereas the heat spreader in the through opening and mechanically supported by the second wiring structure can provide thermal dissipation for the first device. Additionally, attaching the bonding wires to the sub-assembly and the wiring board can offer a reliable connecting channel for interconnecting the devices assembled in the sub-assembly to terminal pads provided in the wiring board.
These and other features and advantages of the present invention will be further described and more readily apparent from the detailed description of the preferred embodiments which follows.
The following detailed description of the preferred embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which:
Hereafter, examples will be provided to illustrate the embodiments of the present invention. Advantages and effects of the invention will become more apparent from the following description of the present invention. It should be noted that these accompanying figures are simplified and illustrative. The quantity, shape and size of components shown in the figures may be modified according to practical conditions, and the arrangement of components may be more complex. Other various aspects also may be practiced or applied in the invention, and various modifications and variations can be made without departing from the spirit of the invention based on various concepts and applications.
Referring now to
The conductive traces 217 can be deposited as a single layer or multiple layers by any of numerous techniques, such as electroplating, electroless plating, evaporating, sputtering, or their combinations. For instance, they can be deposited by first dipping the structure in an activator solution to render the dielectric layer 215 catalytic to electroless copper, and then a thin copper layer is electrolessly plated to serve as the seeding layer before a second copper layer is electroplated on the seeding layer to a desirable thickness. Alternatively, the seeding layer can be formed by sputtering a thin film such as titanium/copper before depositing the electroplated copper layer on the seeding layer. Once the desired thickness is achieved, the plated layer can be patterned to form the conductive traces 217 by any of numerous techniques such as wet etching, electro-chemical etching, laser-assist etching, or their combinations, with an etch mask (not shown) thereon that defines the conductive traces 217.
At this stage, the formation of a routing circuitry 21 on the sacrificial carrier 10 is accomplished. In this illustration, the routing circuitry 21 is a multi-layered buildup circuitry and includes routing traces 212, a dielectric layer 215 and conductive traces 217.
At this stage, a stacked semiconductor sub-assembly 20 is accomplished and includes a routing circuitry 21, a first device 22, a molding compound 25, and a second device 27. The first device 22 and the second device 27 are electrically coupled to first and second surfaces 201, 202 of the routing circuitry 21, respectively, and the molding compound 25 is disposed over the first surface 201 and laterally surrounds the first device 22.
At this stage, a wiring board 30 is accomplished and includes a first wiring structure 31, a heat spreader 35 and a second wiring structure 36. As the depth of the through opening 315 is more than the thickness of the heat spreader 35, the exterior surface of the heat spreader 35 and the sidewall surface of the through opening 315 of the first wiring structure 31 forms a cavity 316 in the through opening 315 of the first wiring structure 31. As a result, the heat spreader 35 can provide thermal dissipation for a device accommodated in the cavity 316, whereas the combination of the first wiring structure 31 and the second wiring structure 36 offers electrical contacts for next connection from two opposite sides of the wiring board 30.
Accordingly, as shown in
The first device 22 is flip-chip electrically coupled to the routing circuitry 21 from one side of the routing circuitry 21 and enclosed by the molding compound 25 and the heat spreader 35. The second device 27 is flip-chip electrically coupled to the routing circuitry 21 from the other side of the routing circuitry 21 and face-to-face connected to the first device 22 through the routing circuitry 21. As such, the routing circuitry 21 offers primary fan-out routing and the shortest interconnection distance between the first device 22 and the second device 27. The heat spreader 35 of the wiring board 30 is thermally conductible to and covers the first device 22 from below. The first wiring structure 31 laterally surrounds peripheral edges of the stacked semiconductor sub-assembly 20 and the heat spreader 35, and is electrically coupled to the routing circuitry 21 by the bonding wires 41. The second wiring structure 36 covers the first wiring structure 31 and the heat spreader 35 from below, and is electrically coupled to the first wiring structure 31 and thermally conductible to the heat spreader 35 through metallized vias 364. As a result, the routing circuitry 21, the first wiring structure 31 and the second wiring structure 36 can provide staged fan-out routing for the first device 22 and the second device 27.
For purposes of brevity, any description in Embodiment 1 above is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
Accordingly, as shown in
The first device 22 and the second device 27 are disposed at two opposite sides of the routing circuitry 21 and face-to-face electrically connected to each other through the routing circuitry 21 therebetween. As such, the routing circuitry 21 offers the shortest interconnection distance between the first device 22 and the second device 27, and provides first level fan-out routing for the first device 22 and the second device 27. The heat spreader 35 covers the inactive surface of the first device 22 and is thermally conductible to the first device 22, whereas the metal layer 37 surrounds peripheral edges of the stacked semiconductor sub-assembly 20 and contacts the heat spreader 35. The first wiring structure 31 is electrically coupled to the routing circuitry 21 through bonding wires 41. The second wiring structure 36 covers the first wiring structure 31 and the heat spreader 35 from below, and is electrically coupled to the first wiring structure 31 for signal routing and to the heat spreader 35 for ground connection through metallized vias 364. Accordingly, the combination of the first wiring structure 31 and the second wiring structure 36 can provide second level fan-out routing for the routing circuitry 21 and electrical contacts for next-level connection, whereas the combination of the heat spreader 35 and the metal layer 37, electrically connected to the second wiring structure 36, provides thermal dissipation and EMI shielding for the first device 22.
For purposes of brevity, any description in Embodiments above is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
The first device 22/passive component 23 and the second device 27 are disposed at two opposite sides of the routing circuitry 21 and face-to-face electrically connected to each other through the routing circuitry 21 therebetween. The metal pillar 24 is electrically connected to the routing circuitry 21 and extends through the molding compound 25. The heat spreader 35 is electrically connected to the metal pillar 24 for ground connection and thermally conductible to the first device 22 for heat dissipation. The combination of the first wiring structure 31 and the second wiring structure 36 is electrically coupled to the routing circuitry 21 using the bonding wires 41, and electrically coupled to the heat spreader 35 through metallized vias 364. The vertical connecting elements 58 are mounted on and electrically coupled to the first wiring structure 31 and laterally surrounded by the encapsulant 51.
For purposes of brevity, any description in Embodiments above is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
The semiconductor assembly 510 is similar to that illustrated in
The semiconductor assembly 610 is similar to that illustrated in
The semiconductor assemblies described above are merely exemplary. Numerous other embodiments are contemplated. In addition, the embodiments described above can be mixed-and-matched with one another and with other embodiments depending on design and reliability considerations. For instance, the first wiring structure may have multiple through openings in an array and each stacked semiconductor sub-assembly is accommodated in its corresponding through opening. Also, the first wiring structure of the wiring board can include additional conductive traces to receive and route additional stacked semiconductor sub-assemblies.
As illustrated in the aforementioned embodiments, a distinctive semiconductor assembly is configured and includes a stacked semiconductor sub-assembly electrically coupled to a wiring board by bonding wires. Optionally, an encapsulant may be further provided to cover the bonding wires. For the convenience of below description, the direction in which the first surfaces of the routing circuitry and the first wiring structure face is defined as the first direction, and the direction in which the second surfaces of the routing circuitry and the first wiring structure faces is defined as the second direction.
The stacked semiconductor sub-assembly includes a first device, a second device, a routing circuitry and optionally a molding compound, and may be prepared by the steps of: electrically coupling the first device to the first surface of the routing circuitry detachably adhered over a sacrificial carrier by, for example, bumps; optionally providing the molding compound over the routing circuitry; removing the sacrificial carrier from the routing circuitry; and electrically coupling the second device to the second surface of the routing circuitry by, for example, bumps or bonding wires. As a result, the first and second devices, respectively disposed over the first and second surfaces of the routing circuitry, can be electrically connected to each other by the routing circuitry.
The first and second devices can be semiconductor chips, packaged devices, or passive components. The first device can be electrically coupled to the routing circuitry by a well-known flip chip bonding process with its active surface facing in the routing circuitry using bumps without metallized vias in contact with the first device. Likewise, after removal of the sacrificial carrier, the second device can be electrically coupled to the routing circuitry by a well-known flip chip bonding process with its active surface facing in the routing circuitry using bumps without metallized vias in contact with the second device. Alternatively, the second device is electrically coupled to the routing circuitry by wire bonding process with its active surface facing away the routing circuitry.
The routing circuitry can be a buildup circuitry without a core layer to provide primary fan-out routing/interconnection and the shortest interconnection distance between the first and second devices. Preferably, the routing circuitry is a multi-layered buildup circuitry and can include at least one dielectric layer and conductive traces that fill up via openings in the dielectric layer and extend laterally on the dielectric layer. The dielectric layer and the conductive traces are serially formed in an alternate fashion and can be in repetition when needed. Accordingly, the routing circuitry can be formed with electrical contacts at its first and second surfaces for first device connection from the first surface and second device connection and next-level connection from the second surface.
The wiring board includes a heat spreader, a first wiring structure and a second wiring structure. The first wiring structure includes electrical contacts at its second surface for the routing circuitry connection from the second direction, whereas the second wiring structure includes electrical contacts at its exterior surface for next-level connection from the first direction. The first wiring structure has a through opening extending from its first surface to its second surface to accommodate the heat spreader and the stacked semiconductor sub-assembly therein. The first wiring structure is not limited to a particular structure, and may be a multi-layered routing circuitry that laterally surround peripheral edges of the first device, the optional molding material and the heat spreader. For instance, the first wiring structure may include an interconnect substrate, a first buildup circuitry and a second buildup circuitry. The first and second buildup circuitries are disposed on both opposite sides of the interconnect substrate. The interconnect substrate can include a core layer, first and second routing layers respectively on both opposite sides of the core layer, and metallized through vias formed through the core layer to provide electrical connection between the first and second routing layers. Each of the first and second buildup circuitries typically includes a dielectric layer and one or more conductive traces. The dielectric layers of the first and second buildup circuitries are respectively deposited on opposite sides of the interconnect substrate. The conductive traces extend laterally on the dielectric layer and include conductive vias in contact with first and second routing layers of the interconnect substrate. Further, the first and second buildup circuitries can include additional dielectric layers, additional via openings, and additional conductive traces if needed for further signal routing. Accordingly, the outmost conductive traces at both the first and second surfaces of the first wiring structure can provide electrical contacts for the routing circuitry connection from its second surface and for the second wiring structure connection from its first surface. The second wiring structure is provided to cover the backside surface of the heat spreader and the first surface of the first wiring structure, and is electrically coupled to the heat spreader and the first wiring structure by metallized vias embedded in a dielectric layer of the second wiring structure and in contact with the backside surface of the heat spreader and the first surface of the first wiring structure. Accordingly, the heat spreader, covered by the dielectric layer of the second wiring structure from the first direction, can be mechanically supported by the second wiring structure and provide thermal dissipation and EMI shielding for the first device attached thereto using a thermally conductive material. As the heat spreader has a thickness less than that of the first wiring structure, a cavity is formed in the wiring board to accommodate the stacked semiconductor sub-assembly therein. Preferably, the heat spreader is a metal layer having peripheral edges adjacent to and attached to sidewalls of the through opening of the first wiring structure. Optionally, an additional metal layer may be further provided in contact with the heat spreader and the sidewalls of the through opening of the first wiring structure and completely cover a remaining portion of sidewalls of the through opening of the first wiring structure. The second wiring structure may be a multi-layered routing circuitry and laterally extends to peripheral edges of the first wiring structure. Preferably, the second wiring structure is a multi-layered buildup circuitry without a core layer, and includes dielectric layers and conductive traces in repetition and alternate fashion. The conductive traces include metallized vias in the dielectric layer and extend laterally on the dielectric layer. The outmost conductive traces of the first and second wiring structures can respectively accommodate conductive joints, such as solder balls or bonding wires, for electrical communication and mechanical attachment with an assembly, an electronic device, an additional heat spreader, an additional wiring board or others. For instance, a third device may be a semiconductor chip and mounted over and electrically coupled to the second wiring structure through a plurality of bonding wires, or be a ball grid array package or a bumped chip and mounted over and electrically coupled to the first wiring structure or the second wiring structure through a plurality of solder balls. As another aspect of the present invention, an additional heat spreader may be mounted over the second surface of the first wiring structure, and the second device can be disposed in a cavity of the additional heat spreader and thermally conductible to the additional heat spreader through a thermally conductive material. Further, the additional heat spreader may be electrically coupled to the first wiring structure for ground connection by, for example, solder balls in contact with the additional heat spreader and the outmost conductive traces of the first wiring structure. Alternatively, an additional wiring board may be stacked over the stacked semiconductor sub-assembly and the wiring board and electrically coupled to the first wiring structure from the second surface of the first wiring structure. More specifically, the additional wiring board can include a third wiring structure, a fourth wiring structure and an additional heat spreader. The third wiring structure has a through opening extending from its first surface to its second surface to accommodate the additional heat spreader and the second device therein. Preferably, the third wiring structure is a multi-layered routing circuitry and laterally surround peripheral edges of the additional heat spreader and a selected portion of the sub-assembly outside of the through opening. For instance, the third wiring structure may include an interconnect substrate having a core layer, routing layers respectively on both opposite sides of the core layer, and metallized through vias formed through the core layer to provide electrical connection between both the routing layers. Alternatively, the third wiring structure may be a multi-layered buildup circuitry without a core layer, and includes dielectric layers and conductive traces in repetition and alternate fashion. In any case, the third wiring structure can include electrical contacts at its opposite first and second surfaces for electrical connection with the first wiring structure and with the fourth wiring structure. Accordingly, the third wiring structure can be electrically coupled to the first wiring structure by, for example, solder balls, between the second surface of the first wiring structure and the first surface of the third wiring structure, whereas the fourth wiring structure can be electrically coupled to the second surface of the third wiring structure by metallized vias. Further, the fourth wiring structure is also electrically coupled to the heat spreader disposed in the through opening of the third wiring structure by metallized vias for ground connection. As a result, when the second device of the sub-assembly is disposed in the through opening of the third wiring structure, the heat spreader of the additional wiring board can provide thermal dissipation and EMI shielding for the second device attached thereto using a thermally conductive material. Preferably, the fourth wiring structure is a multi-layered routing circuitry and laterally extends to peripheral edges of the third wiring structure. For instance, the fourth wiring structure may be a multi-layered buildup circuitry without a core layer, and include dielectric layers and conductive trace in repetition and alternate fashion. As a result, the fourth wiring structure can include conductive traces at its exterior surface to provide electrical contacts from the second direction, and a third device may be optionally stacked over and electrically coupled to the exterior surface of the fourth wiring structure. Additionally, when the stacked semiconductor sub-assembly is an optical sub-assembly, a lens optically transparent to at least one range of light wavelengths may be stacked over the sub-assembly and mounted on the first wiring structure of the wiring board.
The bonding wires provide electrical connections between the routing circuitry of the sub-assembly and the first wiring structure of the wiring board. In a preferred embodiment, the bonding wires contact and are attached to the second surface of the routing circuitry exposed from the through opening of the first wiring structure and the second surface of the first wiring structure. As a result, the first and second devices can be electrically connected to the wiring board for external connection through the routing circuitry and the bonding wires.
Optionally, an array of vertical connecting elements may be further provided in electrical connection with the wiring board for next-level connection. Preferably, the vertical connecting elements contact and are electrically coupled to the first wiring structure from the second surface of the first wiring structure. The vertical connecting elements can include metal posts, solder balls or others, and may be laterally covered by an encapsulant. As the vertical connecting elements have a selected portion not covered by the encapsulant, a third device can be further provided to be electrically coupled to the vertical connecting elements.
The term “cover” refers to incomplete or complete coverage in a vertical and/or lateral direction. For instance, in a preferred embodiment, the heat spreader covers the first device in the first direction regardless of whether another element such as the thermally conductive material is between the first device and the heat spreader.
The phrases “attached to”, “attached on”, “mounted to” and “mounted on” includes contact and non-contact with a single or multiple element(s). For instance, in a preferred embodiment, the peripheral edges of the heat spreader are attached to the sidewalls of the through opening regardless of whether the peripheral edges of the heat spreader contact the sidewalls of the through opening or are separated from the sidewalls of the through opening by an adhesive.
The phrases “electrical connection”, “electrically connected” and “electrically coupled” refer to direct and indirect electrical connection. For instance, in a preferred embodiment, the bonding wires directly contact and are electrically connected to the first wiring structure, and the routing circuitry is spaced from and electrically connected to the first wiring structure by the bonding wires.
The “first direction” and “second direction” do not depend on the orientation of the semiconductor assembly, as will be readily apparent to those skilled in the art. For instance, the first surfaces of the routing circuitry and the first wiring structure face the first direction and the second surfaces of the routing circuitry and the first wiring structure face the second direction regardless of whether the semiconductor assembly is inverted. Thus, the first and second directions are opposite one another and orthogonal to the lateral directions. Furthermore, the first direction is the upward direction and the second direction is the downward direction when the outer surface of the second wiring structure faces in the upward direction, and the first direction is the downward direction and the second direction is the upward direction when the outer surface of the second wiring structure faces in the downward direction.
The semiconductor assembly according to the present invention has numerous advantages. For instance, the first and second devices are mounted on opposite sides of the routing circuitry, which can offer the shortest interconnect distance between the first and second devices. The routing circuitry provides primary fan-out routing/interconnection for the first and second devices, whereas the wiring board provides a second level fan-out routing/interconnection. As the routing circuitry of the sub-assembly are connected to the first wiring structure of the wiring board by bonding wires, not by direct build-up process, the simplified process steps result in lower manufacturing cost. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier for the first device. The second wiring structure can provide mechanical support for the heat spreader and dissipate heat from the heat spreader. The semiconductor assembly made by this method is reliable, inexpensive and well-suited for high volume manufacture.
The manufacturing process is highly versatile and permits a wide variety of mature electrical and mechanical connection technologies to be used in a unique and improved manner. The manufacturing process can also be performed without expensive tooling. As a result, the manufacturing process significantly enhances throughput, yield, performance and cost effectiveness compared to conventional techniques.
The embodiments described herein are exemplary and may simplify or omit elements or steps well-known to those skilled in the art to prevent obscuring the present invention. Likewise, the drawings may omit duplicative or unnecessary elements and reference labels to improve clarity.
This application is a continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016, a continuation-in-part of U.S. application Ser. No. 15/289,126 filed Oct. 8, 2016, a continuation-in-part of U.S. application Ser. No. 15/353,537 filed Nov. 16, 2016, a continuation-in-part of U.S. application Ser. No. 15/415,844 filed Jan. 25, 2017, a continuation-in-part of U.S. application Ser. No. 15/415,846 filed Jan. 25, 2017 and a continuation-in-part of U.S. application Ser. No. 15/462,536 filed Mar. 17, 2017. The U.S. application Ser. No. 15/166,185 claims the priority benefit of U.S. Provisional Application Ser. No. 62/166,771 filed May 27, 2015. The U.S. application Ser. No. 15/289,126 is a continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016. The U.S. application Ser. No. 15/353,537 is a continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016 and a continuation-in-part of U.S. application Ser. No. 15/289,126 filed Oct. 8, 2016. The U.S. application Ser. Nos. 15/415,844, 15/415,846 and 15/462,536 are continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016, continuation-in-part of U.S. application Ser. No. 15/289,126 filed Oct. 8, 2016 and continuation-in-part of U.S. application Ser. No. 15/353,537 filed Nov. 16, 2016. The entirety of each of said applications is incorporated herein by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5583377 | Higgins, III | Dec 1996 | A |
| 5790384 | Ahmad et al. | Aug 1998 | A |
| 5801072 | Barber | Sep 1998 | A |
| 5977640 | Bertin et al. | Nov 1999 | A |
| 6084308 | Kelkar et al. | Jul 2000 | A |
| 6091138 | Yu et al. | Jul 2000 | A |
| 6150724 | Wenzel et al. | Nov 2000 | A |
| 6204562 | Ho et al. | Mar 2001 | B1 |
| 6365963 | Shimada | Apr 2002 | B1 |
| 6369448 | McCormick | Apr 2002 | B1 |
| 6376917 | Takeshita et al. | Apr 2002 | B1 |
| 6495910 | Wu | Dec 2002 | B1 |
| 6507115 | Hofstee et al. | Jan 2003 | B1 |
| 6555917 | Heo | Apr 2003 | B1 |
| 6563205 | Fogal et al. | May 2003 | B1 |
| 6586836 | Ma et al. | Jul 2003 | B1 |
| 6659512 | Harper et al. | Dec 2003 | B1 |
| 6768208 | Lin et al. | Jul 2004 | B2 |
| 6844619 | Tago | Jan 2005 | B2 |
| 6861750 | Zhao et al. | Mar 2005 | B2 |
| 6870248 | Shibata | Mar 2005 | B1 |
| 6906408 | Cloud et al. | Jun 2005 | B2 |
| 6984544 | Cloud et al. | Jan 2006 | B2 |
| 7002254 | Harper et al. | Feb 2006 | B2 |
| 7026719 | Wang | Apr 2006 | B2 |
| 7087988 | Hosomi | Aug 2006 | B2 |
| 7198980 | Jiang et al. | Apr 2007 | B2 |
| 7202559 | Zhao et al. | Apr 2007 | B2 |
| 7205646 | Lin et al. | Apr 2007 | B2 |
| 7218005 | Tago | May 2007 | B2 |
| 7462933 | Zhao et al. | Dec 2008 | B2 |
| 7554194 | Kelly et al. | Jun 2009 | B2 |
| 7573136 | Jiang et al. | Aug 2009 | B2 |
| 7592689 | Brunnbauer | Sep 2009 | B2 |
| 7859120 | Choi et al. | Dec 2010 | B2 |
| 7919853 | Lee | Apr 2011 | B1 |
| 7944043 | Chung et al. | May 2011 | B1 |
| 8008121 | Choi et al. | Aug 2011 | B2 |
| 8022555 | Hwang et al. | Sep 2011 | B2 |
| 8035216 | Skeete | Oct 2011 | B2 |
| 8143097 | Chi et al. | Mar 2012 | B2 |
| 8148806 | Lin et al. | Apr 2012 | B2 |
| 8188379 | Hsu | May 2012 | B2 |
| 8227904 | Braunisch et al. | Jul 2012 | B2 |
| 8288854 | Weng et al. | Oct 2012 | B2 |
| 8421222 | Lin et al. | Apr 2013 | B2 |
| 8519537 | Jeng et al. | Aug 2013 | B2 |
| 8525317 | Sutardja | Sep 2013 | B1 |
| 8558395 | Khan et al. | Oct 2013 | B2 |
| 8648469 | Choi et al. | Feb 2014 | B2 |
| 8686558 | Zhao et al. | Apr 2014 | B2 |
| 8836115 | St. Amand et al. | Sep 2014 | B1 |
| 8971053 | Kariya et al. | Mar 2015 | B2 |
| 9048306 | Chi et al. | Jun 2015 | B2 |
| 9196575 | Lee | Nov 2015 | B1 |
| 9252032 | Choi et al. | Feb 2016 | B2 |
| 9252130 | Kim et al. | Feb 2016 | B2 |
| 9263332 | Chi et al. | Feb 2016 | B2 |
| 9281300 | Merilo et al. | Mar 2016 | B2 |
| 9305897 | Choi et al. | Apr 2016 | B2 |
| 9337161 | Camacho et al. | May 2016 | B2 |
| 9379078 | Yu et al. | Jun 2016 | B2 |
| 9385095 | Jeng et al. | Jul 2016 | B2 |
| 20110024888 | Pagaila | Feb 2011 | A1 |
| 20130052775 | Kim | Feb 2013 | A1 |
| 20140210107 | Zhai | Jul 2014 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20170207200 A1 | Jul 2017 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62166771 | May 2015 | US |
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| Parent | 15166185 | May 2016 | US |
| Child | 15353537 | US | |
| Parent | 15166185 | May 2016 | US |
| Child | 15289126 | US |
