Patent Application
20100103634
The present invention relates to a functional-device-embedded circuit board, a method for manufacturing the same and an electronic equipment and, more particularly, to a functional-device-embedded circuit board that embeds therein one or a plurality of functional devices, a method for manufacturing the same, and an electronic equipment that includes the functional-device-embedded board.
A functional-device-embedded circuit board (hereinafter, may be simply referred to as circuit board) is a circuit board that embeds therein a functional device, such as an LSI. Since the circuit board can avoid more likely application of a mechanical stress onto the electrode portion of the functional device, as compared to other mounting techniques, such as a wire bonding and a flip-chip bonding, that directly connect the functional device to the printed-circuit board, damage to the electrode portion can be suppressed to thereby improve the reliability. In addition, since the electrode portion of the functional device is not exposed on the surface, corrosion of the electrode portion can be suppressed.
The circuit board described in JP-1999-233678A is used as an IC package, wherein a dielectric film having a cavity therein is formed on a metal plate, a semiconductor device is mounted within the cavity on the metal plate, with the active surface thereof on which the electrode terminals are provided being upward, i.e., in a so-called face-up, and a plurality of build-up wiring layers are formed thereon using a photosensitive resin. In the case of using the photosensitive resin, inclusion of silica fillers or glass cloth causes a loss of resolution whereby a sufficient amount of resin for maintaining the strength reliability cannot be used, to thereby incur a problem in that reliability as the package is lost. In addition, since the build-up wiring is formed only on the surface of the semiconductor device including the electrode terminals, the conductive-wiring layers are only formed on the one side to cause an inconvenience that it cannot be used as the circuit board other than the package. Furthermore, the package attached with the metal plate has a heavy weight and a larger external thickness if it is the semiconductor package that does not need heat radiation.
The circuit board described in JP-2002-359324A is formed as a semiconductor package, wherein a semiconductor device including protruding electrodes and a mold substrate having a protrusion at the portion corresponding to the protruding electrodes of the semiconductor device are opposed to each other and bonded together, the gap between the semiconductor device and the mold substrate is filled with fluid resin, and solder balls are formed in the recess formed on the resin overlying the protruding electrodes obtained by removing the mold substrate after curing the resin. The semiconductor package, if it must be formed to have the same size as the semiconductor device and the wiring rule of the semiconductor device is of a narrow pitch, inhibits the wiring rule from being increased and thus causes a problem in that it cannot be used for surface mounting etc. Furthermore, there occurs a deviation upon bonding together the mold substrate and the protruding electrodes, to thereby cause a risk that an opening area above the protruding electrodes is narrower, and incur a problem in that the wettability of the solder balls is degraded. The protruding electrodes, which are formed only on the side of electrode terminals of the semiconductor device, do not have a function of interconnections, thereby causing an inconvenience that it cannot be used as the circuit board.
In the circuit board described in JP-2003-229512A, BGA electrode pads are formed in advance on a metal mold plate, a semiconductor device is connected onto the build-up conductive wiring by flip-chip bonding, flow of under-fill resin is supplied, a board to which the semiconductor device is connected is encapsulated with mold resin, and thereafter the metal mold plate is removed to expose the BGA electrode pads on the surface to obtain the semiconductor package. In this case, since the interconnections are formed only on one side of the semiconductor device near the electrode terminals, i.e., the conductive-wiring layer is formed only on a single surface of the package, it cannot be used as the circuit board other than time package. Moreover, a metal heat sink cannot be attached onto the rear surface of the semiconductor chip, a heat radiation effect cannot be expected. Furthermore, since the semiconductor device is connected by an ordinary flip-chip bonding after forming the conductive-wiring layer of the circuit board, manufacture of the circuit board as well as mounting of the semiconductor device is costly similarly to an ordinary case, whereby a cost reduction cannot be expected.
In the circuit board described in JP-2002-064178A, a semiconductor device is connected to the circuit board by a flip-chip bonding etc., and a plurality of this type of boards are stacked alternately with circuit boards including therein via-plugs obtained by filling a cavity with conductive paste, and solder balls are attached onto the bottom substrate, to obtain a semiconductor-stacked package. In this case, the configuration wherein the boards including the cavity and semiconductors are alternately stacked one on another causes a problem in that an organic resin layer having little rigidity is formed on both the top and bottom of the semiconductor device, whereby fragile semiconductor silicon or GaAs is split at once by application of a pressure thereto. The resin layer on which the chip is mounted is subjected to formation of interconnections while using a copper sheet affixed onto one side thereof, whereby the interconnections are formed by an etching to cause a problem in that narrow-pitch wiring cannot be provided within the package, unlike the case of a semi-additive technique. Due to the configuration wherein the semiconductor device is connected by a flip-chip bonding, manufacture of the circuit board and mounting the semiconductor is costly as in an ordinary case, whereby a problem occurs that cost reduction cannot be expected.
In the circuit board described in JP-2005-217205A, semiconductor devices are stacked one on another using semiconductor chips and spacer chips including therein via-holes. In this case, since the interconnections cannot be spread to excess the size of the semiconductor, and the structure is such that the conductive-wiring layer is exposed only on one side of the package board, there is a defect that it is only used as a package, and cannot be used as a circuit board. In addition, the interconnection distance with respect to the other electronic parts is extremely long due to the connection via a mother board in a surface mounting, thereby incurring a problem in that a high-speed electric performance cannot be obtained as a product, although the high-speed electric performance is excellent only within the package.
In the circuit boards described in JP-2001-332863A, JP-2001-339165A, JP-2001-352174A, JP-2002-084074A, JP-2002-170840A and JP-2002-246504A, through-holes are formed in the core board, a semiconductor chip is mounted therein by using adhesive with the active surface being upward in a face-up, and conductive-wiring layers are stacked on the electrode terminals. Via-holes are formed in the core board, and wiring layers are stacked on both the surfaces of the core board by using a semi-additive technique. In addition, the semiconductor device is mounted on a metal or ceramic heat sink in a face-up, and conductive-wiring layers are stacked onto the electrode terminals. Since a portion of organic resin is only the element located right under the location of through-holes of the core board on which the semiconductor chip is to be mounted, there is a problem in that the semiconductor chip may be split due to a pressure applied during mounting the semiconductor chip because of the bending moment being applied onto the soft resin if a thin chip that is thinner than around 100 μm is used. In addition, if the via-holes am formed in the resin core board embedding therein a semiconductor chip by using a drill etc., there occurs a problem in that a muss is applied onto the semiconductor chip embedded in the vicinity of the via-holes to split the chip due to an insufficient rigidity of the resin during the drilling process. Thus, the via-holes must be significantly apart from the embedded semiconductor chip, thereby increasing the outer size of the board. The product wherein the semiconductor chip is mounted on a metal or ceramic heat sink in a face-up structure and conductive-wiring layers are stacked on the electrode terminals has a drawback that the conductive-wiring layers are formed only on one side thereof, conductive-wiring layers are not provided on the side near the heat sink, and thus cannot be used as the circuit board.
The circuit board described in JP-2006-339421A is such that the semiconductor chip, which is obtained by forming Au stud bumps or solder bumps etc. after forming a dielectric film and a conductor layer on a supporting substrate in a build-up technique, is subjected to a so-called flip-chip process in a face-down structure by coupling the bumps to the conductive wiring on the supporting substrate, thereafter subjected to reinforcement using under-filling, the circumference of the connected semiconductor chip is covered by resin, and thereafter formation of vias, dielectric films and conductor layers is performed by using a build-up technique. The total cost in this process for forming the semiconductor-chip-embedded board is not reduced below the total cost that includes the cost for forming the board, the cost for coupling process in a flip-chip bonding and the cost for the under-filling, as compared to the conventional case where the semiconductor chip is bonded onto the circuit board by using a flip-chip, due to the fact that the semiconductor chip embedded in the board is bonded by flip-chip bonding. Thus, there is a problem in that the process cannot reduce the cost. In addition, due to use of the flip-chip technique, it is needed to apply a heat stress onto the dielectric film at a high temperature of around 300° for about 30 seconds during bonding the bump onto the conductive wiring on the supporting substrate if the Au stud bumps are used, thereby causing degradation of resin and the problem of decrease in the reliability of products. If solder is used for the bumps, the bonding portion itself has the problem in heat resistance, thereby causing the problem of breakage of bump-bonded portion in the semiconductor-chip-embedded board, due to a reflow treatment during the surface mounting, thereby causing a lower reliability of products. On the surface of the semiconductor chip opposing the supporting substrate, the conductive wiring is not flat, thereby incurring a defect that the later mounting process using the semiconductor-chip-embedded board proves a poor workability.
In the circuit board described in JP-2005-236039A, a positioning pattern is formed on the side surface of chip by using a conductive wiring in the vicinity of a position of the transfer substrate on which the semiconductor chip is to be mounted. However, if the positioning pattern is larger than the size of the mounted chip, the chip moves after the mounting, thereby causing the problem of deviation of the chip-mounted position. If the positioning pattern is equivalent to the chip size, the chip may collide with the positioning pattern during mounting the chip by using a mounting device, to incur split of the chip and thus decrease the reliability of products. If adhesive is used on the position on which the chip contacts the transfer substrate, the positioning mark does not have a function of preventing the chip movement in the horizontal direction. Thus, there is the problem of deviation occurring in the positional relationship between the vias positioned on the side surface of chip and the electrode terminals of chip. After removing the transfer substrate, the bottom surface of chip is exposed, whereby there is a risk that the bending or collision that occurs in the later process may split the chip, thereby causing the problem in the reliability and yield of products. On the surface through which the surface of IC chip is exposed, the surface of wiring pattern is flush with the resin layer on the side surface thereof, whereby there occurs a short-circuit failure in the wiring during the solder bonding if the solder resist layer is not provided. If post electrodes are to be provided on the side surface of chip, Cu posts are formed in advance by plating, embedded within resin and then subjected to post grinding. At this stage, the shape of vias as viewed from the sectional surface of the board is a trapezoid, wherein the inner diameter thereof is smaller at one end and larger at the other end. Thus, an internal stress occurring in the thickness direction of the board, with the embedded portion of chip being the center, causes the problem of peel-off between the vias and the dielectric resin.
The circuit board described in JP-2006-19342A has the problem that a mounting process using the conductive wiring formed on both the surfaces cannot be performed because a metal shield layer and a magnetic-body shield layer are formed on one of the surfaces of the IC-chip-embedded board. In addition, since the entire surface opposing the electrode terminals of IC chip directly contacts a mound pattern layer, the chip is warped by the difference in the thermal coefficient of expansion between the Si chip and the metal configuring the ground, thereby causing split of the chip if the chip is thin.
In JP-2001-250902A and JP-2001-237632A, the chip-embedded boards in which a conductor layer is formed only on one of the front and rear surfaces thereof are connected together through both the chips by using the multilevel interconnections. However, since vias cannot be provided in the vicinity of chips, the line length is increased to thereby cause the problem in the high-speed electric performance.
In the above conventional circuit boards, there are problems as recited hereinafter. The problems are such that when a functional device is to be embedded and if the circuit board including an organic resin as a base material and having no supporting substrate is used to underlie the mounting surface of the functional device, the portion of the organic resin of the circuit board is inflected due to the mounting load, thereby generating a bending stress on the functional device itself to damage the device if the functional device itself is comprised of silicon, ceramic etc.
The present invention is devised in view of the problems as described above, and it is an object of the present invention to realize the improvement in the reliability of products and reduction in the cost in relation to formation and mounting of the circuit board by allowing the connection of the functional device to the circuit board and formation of the circuit board to be performed simultaneously with each other.
The present invention provides, in a first aspect thereof, a circuit board including: at least one functional device; a wiring board embedding therein the functional device; and first and second wiring layers disposed on front and rear surfaces of the circuit board to sandwich therebetween the functional device and each including at least one conductor layer, wherein: each of patterned interconnections in an outermost layer of the first conductive-wiring layer is exposed, and a first dielectric layer that isolates the patterned interconnections in the outermost layer has a surface protruding from a surface of the patterned interconnections; and the patterned interconnections in the second wiring layer is connected to electrode terminals of the functional device, and at least a part of a surface of a second dielectric layer isolating the electrode terminals from one another and at least a part of a surface of the electrode terminals are substantially in a same plane.
The present invention provides, in a second aspect thereof, a circuit board wherein the circuit board and a wiring board are stacked one on another in a thickness direction, and a wiring layer of the circuit board and a wiring layer of the wiring board are connected together by a conductive paste or lead-free solder paste including at least one species of element selected from the group consisting of Sn, Ag, Cu, Bi, Zn and Pb.
The present invention provides, in a third aspect thereof, an electronic equipment including the above circuit board.
The present invention provides, in a fourth aspect thereof, a circuit-board manufacturing method including the steps of forming at least one first conductive-wiring layer on a supporting substrate; mounting a functional device on the first conductive-wiring layer, covering the functional device by a dielectric resin layer; removing an upper part of the dielectric resin layer so that the surface of the dielectric resin layer is flush with a surface of the electrode terminals of the functional device; forming a second conductive-wiring layer that is a conductive-wiring layer connected the electrode terminals, and removing the supporting substrate.
The present invention provides, in a fifth aspect thereof, a circuit-board manufacturing method including the step of opposing two of the circuit boards manufactured by the above method against each other, and connecting together both the circuit boards by using an adhesive layer obtained by embedding conductive paste or solder paste within the via-hole.
The present invention provides, in a sixth aspect thereof, a circuit-board manufacturing method including the steps of opposing the functional-device board manufactured by the above method against a wiring board, and connecting together both the circuit boards by using an adhesive layer obtained by embedding conductive paste or solder paste within the via-hole.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
a) to 20(h) are sectional views of respective fabrication stages in a first exemplary embodiment of the circuit-board manufacturing process of the present invention.
a) to 21(j) are sectional views of respective fabrication stages in second exemplary embodiment of the circuit-board manufacturing process of the present invention.
a) to 22(d) are sectional views of respective fabrication stages in a third exemplary embodiment of the circuit-board manufacturing process of the present invention.
a) to 23(d) are sectional views of respective fabrication stages in a fourth exemplary embodiment of the circuit-board manufacturing process of the present invention.
a) and 24(b) are sectional views of respective fabrication stages in a fourth exemplary embodiment of the circuit-board manufacturing process of the present invention.
a) and 25(b) are sectional views of respective fabrication stages in a fourth exemplary embodiment of the circuit-board manufacturing process of the present invention.
a) to 32(d) are sectional views of twelfth exemplary embodiments of the circuit board of the present invention.
a) to 33(i) are sectional views of respective fabrication stages in sixth exemplary embodiment of the circuit-board manufacturing process of the present invention.
a) to 34(j) are sectional views respective fabrication stages in a seventh exemplary embodiment of the circuit-board manufacturing method of the present invention.
a) to 35(h) are sectional views of respective fabrication stages in a an eighth exemplary embodiment of the circuit-board manufacturing process of the present invention.
a) to 36(f4) are sectional views of respective fabrication stages in a ninth exemplary embodiment of the circuit-board manufacturing process of the present invention.
Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings.
The configuration wherein the surface of the electrode terminals 53 is formed at the same height as the surface of dielectric resin layer 81 reduces the number of points of inflection on the surface of the electrode terminals 53 and conductive-wiring layer 31, thereby improving the connection reliability between the electrode terminals 53 and the conductive-wiring layer 31. In the process for forming the conductive-wiring layer 31 by using a plating technique, exposure and development of the plating resist is facilitated, thereby improving the positional accuracy between the conductive-wiring layer 31 and the electrode terminals 53. The configuration wherein the seed layer 55 is formed between the electrode terminals 53 and dielectric resin layer 81 and the conductive-wiring layer 31 improves the adhesive strength between those, especially, between the electrode terminals 53 and the conductive-wiring layer 31, thereby improving the reliability of products.
Ti, W, Cr, Pt, Au, Cu, Ni, Ag, Sn and Pd are suitable for the seed layer 55, which is not limited thereto however. Upon forming the seed layer 55 and conductive-wiring layer 31, the seed layer 55 is first formed, followed by forming the plating resist pattern on the seed layer 55. Subsequently, pattern of the conductive-wiring layer 31 is formed using a plating technique in the area in which the plating resist pattern is not formed. Subsequently, the plating resist pattern is peeled off, followed by removing a portion of the seed layer 55 on which the pattern of conductive-wiring layer 31 is not formed by etching using a chemical liquid, thereby exposing the dielectric resin layer 81. The total thickness of the seed layer 55 is preferably 3 μm or smaller for prevention of reduction in the line width.
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Semi-cured resin, resin paste and Ag paste, which are referred to as dielectric attachment film, may be used for the adhesive layer 25. Due to intervention of the adhesive layer 25 between the functional device 10 and the conductive-wiring layer 41, heat can be diffused through the conductive-wiring layer 41 when the functional device 10 generates the heat, thereby improving the reliability of products. “LE-4000” (trademark) and “LE-5000” (trademark) from LINTEC Corp., and “DF402” (trademark) from Hitachi Chemical Co., Ltd. etc. are suitable for the die attachment film, which is not limited thereto however. Liquid resin including epoxy, polyimide, benzocyclobutene etc. may be used as the base material for the adhesive layer 25 instead of the die attachment film.
By forming a uniform pattern having a shape similar to the rear surface of the functional device 10, or uniform pattern having a size larger than the rear surface of the functional device 10 in a portion of the conductive-wiring layer 41 that opposes the rear surface of the functional device 10, a highly efficient heat radiation can be obtained, and at the same time, the functional device 10 can be protected against a stroke from the exterior of board, whereby a highly reliable structure can be obtained. In addition, since the conductive-wiring layer 41 is formed in a pattern as a whole, and has a portion that exposes therefrom the dielectric resin layer 81 at a suitable position, a stress occurring due to the difference in the thermal coefficient of expansion between the functional device 10 and the conductive-wiring layer 41 can be alleviated more effectively as compared to the package obtained by attaching a metal plate having a larger area, such as a heat sink, onto the rear surface of the functional device. Thus, when the circuit board is used as the package, products having a higher reliability and a longer lifetime can be obtained.
One or a plurality of metals, such as copper, nickel, gold, silver, and lead-free solder formed by a plating technique, a printing technique etc., are suitable for the conductive-wiring layers 31 and 41, which are not limited thereto however. It is possible to perform surface-mount of the electronic parts or semiconductor flip-chip bonding onto the pattern of conductive-wiring layers 31 and 41, thereby reducing the board area and the size of products while effectively assuring the area needed for the mounting. In addition, by directly mounting the electronic parts onto the conductive-wiring layer 31 disposed right above the functional device, the distance between the electronic parts and the electrode terminals 53 of the functional device 10 can be reduced, to obtain a superior high-speed electric performance.
Materials including epoxy, polyimide, liquid crystal polymer etc. as the base material are suitable for the dielectric resin layer 81, which is not limited thereto however. Resins including therein an aramid unwoven cloth, an aramid film, a glass cloth, and a silica film are preferred for improving the strength and high-speed transmission property; however, the materials to be included therein are not limited thereto.
In the first comparative example of
In the second comparative example of
Thus, in the present exemplary embodiment, it is determined that the electrode terminals 53 be formed in the functional device 10, the surface of dielectric resin layer 81 is planarized until the electrode terminals 53 are exposed, prior to forming the seed layer 55.
Upon forming the dielectric resin layer 82, a uniform dielectric resin layer is formed on the electrode terminals 53 and dielectric resin layer 81, and thereafter, openings for exposing therethrough the top of electrode terminals 53 are fanned. In order to form the openings having a suitable shape, a material having a superior laser workability or material having a photosensitivity is preferably used for the dielectric resin layer 82.
Due to the use of separate dielectric resin layers, it is possible to use a combination of resins having a higher temperature resistance and a lower temperature resistance, or a combination of an expensive resin and an inexpensive resin, thereby achieving improvement in the reliability of products and a lower cost. In addition, if a dielectric resin layer 83 is formed on the circumference of the electrode terminals 53 of the functional device 10, for example, a resin having a superior adhesiveness with respect to the dielectric resin layer 83 can be selected for the dielectric resin layer 86. The electrode terminals 53, if exposed from the dielectric resin layer 83, can be clearly observed as an alignment mark, to thereby improve the mounting accuracy. On the other hand, if the electrode terminals 53 are embedded within the dielectric resin layer 83, the advantage of surface protection as well as improvement of workability during mounting of the functional device can be obtained. Note that the functional device 10 may be covered by the dielectric resin layer 86 without forming the dielectric resin layer 83 to achieve a cost reduction. The number of dielectric resin layers in the combination is not limited to three.
In the circuit boards 102A and 102B, a pattern is formed also in a portion of the conductive-wiring layer 41 that opposes the rear surface of the functional device 10. By forming the pattern of conductive-wiring layer 41 also directly under the functional device 1, it is possible to perform surface-mounting of electronic parts and bonding of semiconductor flip-chip etc. onto this pattern, thereby increasing the area for mounting and reducing the size of products. Since the dielectric resin layer 84 itself is a resin in the circuit board 102A, the surface of functional device 10 opposite to the electrode terminals 53 is pressed for mounting thereof against the dielectric resin layer 84 while applying heat in a semi-cured state thereof prior to curing, whereby the dielectric resin layer 84 increases the fluidity thereof due to the heat, and closely adheres onto the functional device 10. This obviates an adhesive layer 25 having a thickness of about 2 to 40 μm, to thereby reduce the thickness of the circuit board. Description with respect to the via-holes 61, via-plugs 74 and seed layer 57 is omitted herein for avoiding duplication with the description on the circuit board shown in
Upon forming the via-plugs 74, formation of the conductive-wiring layer 31 may be performed in parallel. Formation of the conductive-wiring layers 31 and 41 and via-plugs 74 after forming the seed layer 57 may preferably use one or a plurality of metals, such as copper, nickel, gold, silver and lead-free solder, without limitation thereto. All the via-holes 61 have the same taper angle, which case facilitates observation of the plated portion in the step of metal plating of the via-holes 61, thereby facilitating judgment of a non-defective plated state or defective portion to improve the quality of products. If the ratio of height to diameter of the via-holes 61 is larger than one, lead-fire solder paste or conductive paste may be used to fill the same by using a printing technique after forming the seed layer 57.
Connection between the conductive-wiring layer 31 on the front side and the conductive-wiring layer 41 on the rear side of the circuit board 41 through the via-plugs 74 with a shortest distance improves the high-speed electric performance up to about 1 GHz or higher between the functional device 10 and the electronic parts mounted on the front and rear sides of the circuit board. Since the conductive-wiring layer 31 and the conductive-wiring layers 41 are connected together through the via-plugs 74, it is possible to stack circuit boards in the vertical direction, to thereby achieve a high-density mounted body. Due to extension of the seed layer 57 on the side surface and bottom surface of the via-holes 61, the adhesive strength between the via-plugs 74 and the conductive-wiring layer 41 is increased, to thereby improve the reliability of products.
On the surface of the conductive-wiring layer 31, it is needed to prevent a short-circuit failure caused by reflow of the lead-free solder or melting of the solder balls 60 upon mounting the electronic parts 12 and functional device 17, such as a second LSI and radio elements, shown in
It is possible to form solder balls 60 on the conductive-wiring layer 31, as shown in
The dielectric elements 22 are formed between the conductive-wiring layer 31 and the vias 15.1 that connect together the conductive-wiring layer 31 and the conductive-wiring layer 31, and include one or more element of Mg, Ti, Sr, Ba, Ca, Zn, Al, Ta, Si, Au, N and O. The inductors 23 are formed as the same layer as the conductive-wiring layer 33, and have a spiral shape or meander shape. In the present exemplary embodiment, another seed layer other than the seed layer 57 may be provided on the bottom of the via 152, the another seed layer connecting the conductive-wiring layer 33 to the electrode terminals 53 of the functional device 10. These resistors 21, dielectric elements 22, and inductors 23 may be fanned on the rear side of the functional device 10.
In the present exemplary embodiment, inclusion of any one of the above resistors 21, dielectric elements 22, and inductors 23 can reduce the volume of the passive component embedded in or surface-mounted on the circuit board, thereby achieving a superior electric performance. Provision of a plurality of conductive-wiring layers on the front side of the functional device achieves a circuit board having a higher function. The solder resist layer may be formed on the front surface and rear surface of the circuit board.
If the conductive-wiring layer is formed on the front and rear surfaces of the intermediate layer 24, the circuit board may have a larger number of layers to achieve a highly efficient multilevel-wiring board. The solder resist layer may be formed on the front surface and rear surface of the circuit board.
Since the dielectric resin layer 84 itself is a resin, if the surface of functional device 10 opposing the electrode terminals 53 is pressed against the dielectric resin layer 84 in a semi-cured state thereof prior to curing, while applying heat thereto, the dielectric resin layer 84 increases the fluidity due to the heat and closely adheres onto the functional device 10. This obviates the adhesive layer 25 having a thickness of about 2 to 40 μm, to achieve a reduction in the thickness of the circuit board. Note that the shape or material of the copper posts and conductive-wiring layer is not limited. If it is desired to fix the functional device with a strength higher than the strength with which the dielectric resin layer 84 fixes the functional device, the adhesive layer 25 may be used, as shown in
Via-plugs 75 connect together the conductive-wiring layer 33 and the conductive-wiring layer 43, via-plugs 76 connects together the conductive-wiring layer 32 and the conductive-wiring layer 42, via-plugs 77 connects together the conductive-wiring layer 32 and the conductive-wiring layer 43, and via-plugs 78 connect together the conductive-wiring layer 33 and the conductive-wiring layer 42. Via-plugs 14 connect together the conductive-wiring layer 32 and the conductive-wiring layer 33, via-plugs 15 connect together the electrode terminals 53 and the conductive-wiring layer 33, and via-plugs 16 connect together the conductive-wiring layer 42 and the conductive-wiring layer 43. The via-plugs 75 to 78 are comprised of a plating metal, such as copper, nickel, gold and silver, or conductive paste.
Since the via-plugs 75 to 78 connect each conductive-wiring layer to any arbitrary conductive-wiring layer, the design choice of the circuitry is increased. Since the via-plugs 15 connect together the electrode terminals 53 and the conductive-wiring layer 33, the line distance between the electrode terminals 53 of the functional device 10 and the capacitors or semiconductor devices formed outside the circuit board can be reduced. The seed layer 57 is formed between the electrode terminals 53 and conductive-wiring layer 32 and the dielectric resin layer 86 as well as on the side surface and bottom surface of the via-holes 63 and 64.
The surface of the conductive-wiring layer 42 is formed at the same height as the surface of dielectric resin layer 84. As for the conductive-wiring layer 43, the side surface thereof contacts the dielectric resin layer 84.1, and the dielectric resin layer 84.1 is not formed on the top surface thereof. The top surface of the conductive-wiring layer 43 is formed at a height lower than the surface of dielectric resin layer 84.1.
Incorporation of a plurality of functional devices 10 and 17 reduces the line length between the embedded functional devices 10 and 17, to achieve a circuit board that is superior in the high-speed electric performance. A circuit board having a variety of functions is realized by combining radio elements with elements of logic and memory devices, as the functional devices 10 and 17. Since the functional devices 10 and 17 are not exposed on the surface, workability can be improved during the conveyance.
Since the electrode terminals 53 of the functional device 10 oppose those of the functional device 10B, the line length between the functional devices 10 and 10B is reduced, to achieve a circuit board superior in the high-speed electric performance. Since the distance between the surface of the functional devices 10 and 10B and the surface of the circuit boards 305 and 306 is equal between the circuit board 305 and the circuit board 306, if a flip-chip bonding is performed with respect to the LSI, for example, the line distance between the LSI and the electrode terminals 53 of both the functional devices 10 and 10B is equal between the circuit board 305 and the circuit board 306, thereby improving the connection reliability. Although the circuit boards 305 and 306, such as shown in
The structure of connection between the exposed surface of the electrode terminals 53 and the conductive-wiring layer 31 may be such that the conductive-wiring layer 31 exists only right above a portion of the exposed surface of the circular electrode terminals 53, as shown in
In the present exemplary embodiment, provision of the seed layer on the side surface, bottom portion and top portion of the vias prevents internal fracture of the vias, fracture of top portion and bottom portion of the vias, peel-off of the side surface of the vias from the dielectric resin layer, in the event of deformation caused by incorporation of the functional device in the board, thereby achieving highly reliable products. Forming a common layer for the electrode terminals 53 and seed layer 511 facilitates observation of the position during the resist exposure upon forming the wiring pattern of the vias 501 and electrode terminals 53, to obtain a superior positioning accuracy. Thus, the product yield can be improved. In addition, use of the filled vias as the vias 501 reduces the electric resistance to thereby improve the electric properties as compared to the case of using conformal-type ones.
In the present exemplary embodiment, internal fracture of the vias, fracture of the top and bottom portions of the vias and peel-off of the side surface of the vias from the resin layer can be prevented even in the event of deformation of the board caused by incorporation of the functional device 10 in the board, similarly to the circuit board 115 shown in
As a result, in the present exemplary embodiment, a portion of the internal conductor of vias 503 near the conductive-wiring layer 31 and having a large inner diameter may be of a material having a larger crystal-grain diameter and an expanding property, whereby the stress can be alleviated in the event of deformation of the substrate, such as warp of the board caused by embedding the functional device 10. On the other hand, although the internal conductor material of the vias 503 in the vicinity of the conductive-wiring layer 73 and having a smaller inner diameter and a smaller contact area does not have an expanding property, a superior adhesive strength can be obtained with respect to the conductive-wiring layer 73. Therefore, even if the seed layer is not formed at the interface between the side surface of the vias and the dielectric resin layer, disconnection of vias can be avoided by alleviating the stress applied to the interface, thereby improving the reliability of products.
a), 32(b), 32(c) and 32(d) are sectional views of twelfth exemplary embodiments of the circuit board of the present invention. In the circuit boards 118A to 118D, conductor vias that connect together the conductive-wiring layer 31 and the conductive-wiring layer 73 include mushroom-shaped posts (conductor posts) 510 and via-plugs 504, 505, 506 and 507 connected to the mushroom-shaped posts 510. The mushroom-shaped posts 510 have a portion of a substantially uniform diameter, and a large-diameter portion (corresponding to pileus and also referred to as pileus-structured portion) having a larger diameter than the uniform-diameter portion, and are disposed near the conductive-wiring layer 73, as shown in the figure. This pileus-structured portion inserts a wedge onto the dielectric resin layer in the horizontal direction of the board. Laser vias are formed on the mushroom-shaped posts 510 near the conductive-wiring layer 31.
In the circuit board 118A, as shown in
In the present exemplary embodiment, the above pileus-structured portion of the mushroom-shaped posts 510 extends as a wedge within the dielectric resin layer in the horizontal direction (direction substantially perpendicular to the thickness direction) of the dielectric resin layer, whereby the strength between the vias and the dielectric resin layer in the thickness direction can be improved, even without forming the seed layer on the side surface of the vias, for the case of thickness deformation or warping stress occurring in the functional-device-embedded board, to thereby prevent disconnection at the vias. Thus, reliability of products can be improved. On the other hand, for the ordinary vias having a sectional shape of trapezoid, there is a possibility that the via conductor is peeled off from the contacting dielectric resin layer, if reinforcement of adhesion of the side surface of the vias is not employed with respect to the dielectric resin layer by using the seed layer, as in the case of the present exemplary embodiment. Note that circuit boards 118A to 118D may be selected as desired in consideration of the cost of materials and the combination with respect to the materials of the via-plugs 504 to 507. Irrespective of selection of any of those, these circuit boards have a higher reliability, compared to the circuit board without using the mushroom-shaped posts 510, because of using the mushroom-shaped posts 510.
a) to 20(h) are sectional views of respective fabrication stages in a first exemplary embodiment of the circuit-board manufacturing process of the present invention. First, as shown in
A single material, such as Si, glass, aluminum, stainless steel, polyimide, epoxy, or a composite material thereof is preferably used for the supporting substrate 71, which is not limited thereto however. If the supporting substrate 71 is not a conductor material, provision of a plating seed metal by using sputtering or electroless plating allows formation of the conductive-wiring layer 72. If the supporting substrate 71 is removed by a process other than the etching, provision of a releasing material in advance within the material of the supporting substrate 71 is preferred, without limitation thereto. For example, as a releasing layer adhered onto a plate comprised of a single material, such as Si, glass, aluminum, stainless steel, polyimide and epoxy, an ultra thin copper foil with a career, “Micro Thin (MT)” series, including a releasing layer sandwiched between two copper foils and supplied from Mitsui Mining and Smelting Co., Ltd. may be preferably used, and a single-surface releasing tape, “PTFE tape”, supplied form Sumitomo 3M Co. Ltd may be preferably used for the supporting substrate 71. The supporting substrate 71 including a compound material is not limited thereto however.
Subsequently, the conductive-wiring layer 73 is formed to have a predetermined thickness by using a plating technique, without peeling off the plating resist or after peeling off the plating resist and forming another resist pattern, and thereafter the plating resist is peeled off. At this stage, it is preferable that the conductive-wiring layer 73 exist on the conductive-wiring layer 72. Thus, gold, copper, nickel etc. are preferably used, without limitation thereto, for the conductive-wiring layer 73 which is left after removal of the supporting substrate 72. In a subsequent step, as shown in
At this stage, it is preferable to form the pattern of conductive-wiring layer 73 in the area for mounting thereon the device so that a planar metal area is obtained, because the area functions as a heat sink after removal of the supporting substrate 71, without limitation thereto. The functional device 10 is provided in advance with electrode terminals 53 having a cylindrical shape or multilevel wiring structure, or in an alternative, may use Au stud bumps, although the configuration of the electrode terminals 53 is not limited thereto. Materials of the electrode terminals 53 include Cu, Ag, Ni etc., without limitation thereto. If protection of the chip active surface is needed, the dielectric resin layer 83 is provided; however, if there is little problem in the strength, it may be obviated. If the dielectric resin layer 83 is provided, the electrode terminals 53 of the functional device may be embedded, prior to the mounting, within the dielectric resin layer 83 and without being exposed on the surface.
In a subsequent step, as shown in
The number and species of the dielectric resin layers may be judged as desired depending on the thickness of the embedded functional device 10 and the overall thickness of the board, and a single layer may be used. In a subsequent step, as shown in
Thereafter, as shown in
After forming the via-holes 67 in the dielectric resin layers 81 and 85, resin residues within the via-holes 67 are removed by a desmear processing, and at the same time the grinding sludge configured by resin residues existing on the portion of the electrode terminals 53 exposed on the surface can also be removed. The surface of dielectric resin layer 86 has thereon concaves and convexes of 10-μm height or less due to the desmear processing, which have an anchor effect to improve the adhesive strength after forming the conductive-wiring layer 31.
After washing the conductive-wiring layer 73 by using a weak acid, such as dilute sulfuric acid, at least one conductor layer is formed by an electroless plating using copper, nickel etc. or by a sputtering processing using at least one species of element in the group consisting of Ti, W, Cr, Pt, Au, Cu, Ni, Ag, Sn and Pd, and used as the seed layer for subsequent plating step. The technique for forming the seed layer is not limited to the electroless plating or sputtering processing. In a subsequent step; as shown in
In a subsequent step, as shown in
The conductive-wiring layers 72 and 73, which are originally formed on the supporting substrate 71, have a uniform height, are located on the same plane, and can be preferably used as electrode terminals by which the surface mounting is performed in the semiconductor device, BGA package etc., to achieve a high connection reliability. The circuit board thus obtained may be used in this state, or may be used for multi-device mounting, as described hereinafter, after fanning a solder resist layer having arbitrary openings. It is also possible to use the stage shown in
a) to 21(j) are sectional views of respective fabrication stages in a second exemplary embodiment of the circuit-board manufacturing process of the present invention. The conductive-wiring layers 72 and 73 are formed by a plating technique, an inkjet technique etc. on the supporting substrate 71 in
In a subsequent step, as shown in
If the board has a smaller thickness, the intermediate layer 24 comprised of a metal or ceramics has the function of preventing a warp or improving the rigidity. Since a laser processing is performed in a later step for forming vias that connect together the conductive-wiring layer 73 and the conductive-wiring layer 31, if the intermediate layer 24 itself is of a conductor or material for which the laser processing is difficult, it is needed to form openings in an arbitrary position of the intermediate layer 24, which are larger in size than the outer shape of the vias, and an opening having a size equal to or larger than the outer shape of the functional device at the location where the functional device 10 is to be forted.
In a subsequent step, as shown in
After a subsequent desmear processing for washing the resin residues away from the inside of vias, the supporting substrate 71, which is of a metal, may be used to provide electric charge for directly plating the inside of vias on the side near the supporting substrate 71, if the via-holes have a height significantly larger than the inner diameter thereof. However, it is possible to use an electroless metal plating or sputtering treatment, as described with reference to
Note that it is efficient to perform grinding or buff-polishing of the electrode terminals 53 shown in
Subsequent processings, which are similar to those in
a) to 22(d) are sectional views of respective fabrication stages in a third exemplary embodiment of the circuit-board manufacturing process of the present invention. As shown in
Subsequently, as shown in.
a) to 23(d) are sectional views of respective fabrication stages in a fourth exemplary embodiment of the circuit-board manufacturing process of the present invention. As shown in
At this stage, a ceramic part may be embedded in advance within the circuit boards 201 and 202 that embed therein the functional device of the present invention. The embedded ceramic part is connected to the conductive-wiring layer of the circuit board of the present invention via the conductive paste or plating. Thereafter, coupling of the upper board and the lower board of the present invention at the insulator portion by using the adhesive layer 40, and electrical connection using the vias 45 are simultaneously performed by using a pressing technique etc., and if there exists the supporting substrate, the supporting substrate is removed therefrom, thereby obtaining a circuit board wherein layers including the functional device are stacked one on another in the vertical direction, as shown in
The adhesive layer 40 may preferably include epoxy, polyimide, liquid crystal polymer etc. as the base material, and is not limited thereto. An aramid unwoven cloth, an aramid film, a glass cloth, and a silica film may be preferably used as the content material included in the adhesive layer 40 for achieving a higher strength and a higher-speed transmission, and the content material is not limited thereto. The circuit boards of the present invention used for bonding may be bonded together even in the state where the supporting substrate is removed therefrom. If at least one board includes the supporting substrate, an advantage is obtained in that a vacuum pressing can uniformly press the boards, to thereby achieve a higher reliability in the bonding that uses the adhesive layer 40 and vias 45.
The adhesive layer 40 may also be obtained by forming the via-holes by using laser, such as CO2 laser, UV-YAG laser and a drill, in the state where the protective film, such as PET and PEN, is attached in advance onto both the surfaces, and filling the via-holes with powder including elements, such as Sn, Ag, Cu, Si, Ni, Fe, Ge, Mg etc., without limitation of the elements thereto, by printing using solder paste and conductive paste through the protective film, and removing the protective film. Even without the protective film, it is possible to use a metal mask or screen mask for the printing. It is also possible to fill the via-holes with powder by using an ink jet technique.
The adhesive layer 40 may be supplied in advance onto one of the circuit boards of the present invention by using a laminating technique or pressing technique, followed by forming therein vias by using laser etc, and by printing using a protective film, a metal mask or screen mask or filling the via-holes with paste by using ink-jet technique. If the protective film is used, the protective film is removed, and a vacuum pressing is performed to bond together the two circuit boards of the present invention. This may be used as it is, or may be used after forming a solder resist layer having therein arbitrary openings for multi-device mounting.
It is possible to use the state of
By embedding in the larger-sized board 411 only the circuit boards 410 that are judged as non-defective devices in the electric test, the product yield can be increased to thereby reduce the fabrication cost. Further, since the conductive-wiring layer in the circuit boards 410 is connected directly to the electrode terminals 53 of the embedded functional device 10, if the conductive wiring dose not include relatively fine interconnections and thus can be formed using the subtractive technique that provides a lower cost, the step of forming the conductive wiring can be performed at separate two sites thereof to achieve an efficient mass production that achieves a superior product yield and a lower cost, although the semi-additive technique that provides fine conductive wiring is typically employed.
Thereafter, in the step of
Here, in the step shown in
Thereafter, in the step of
Here, in the step shown in
It is possible for the AD process to form a thicker film in a short period of time as compared to the plating. Thus, use of the AD process considerably reduces the fabrication time length, and forms a finer metal structure having smaller crystal grains within a portion of the vias 503 having a smaller inner diameter and located near the conductive-wiring layer 153, and on the other hand, forms a larger crystal-grain diameter within a portion of the vias 503 having a larger inner diameter and located near the conductive-wiring layer 31, as compared to that near the conductive-wiring layer 153, thereby improving the reliability of products. In addition, a concentrated energy is applied to the bottom portion of vias 503, whereby a superior bonding strength is obtained at the bottom portion of vias to achieve a higher reliability.
In the step shown in
Irrespective of any techniques used, since the mushroom-shaped posts 510 are formed in advance to be embedded within the resin, in a subsequent laser processing for forming the via-holes, the post portion embedded within the resin is observed above the conductive-wiring layer 73. Thus, recognition of position with a higher accuracy can be obtained, to thereby improve the product yield. Due to presence of the pileus structure portion in the mushroom-shaped posts 510, a superior strength and improved reliability can be obtained as described before. In addition, since the vias formed by laser have a smaller height, the aspect ratio of vias is reduced, whereby removal of residues on the bottom portion of the vias generated during patterning the resist is facilitated and at the same time, the plating liquid in the plating bath well flows onto the bottom portion of vias to thereby achieve a reliable portion of vias near the conductive-wiring layer 31.
Hereinafter, the present invention will be described more concretely with reference to examples.
A first example according to the first embodiment of the present invention will be described with reference to
Epoxy-based materials that contained glass cloth, that contained an aramid unwoven cloth and that used an aramid film were used as the dielectric resin layer 81. It was also confirmed that polyimide can be used as well. More specifically, prepregs now on the marketed, such as “ABF-GX” from Ajinomoto Co., Inc., and “GEA-679FG” from Hitachi Chemical Co., Ltd. etc., were used. In addition, “PIMEL” from Hitachi Chemical Co., Ltd. that is in liquid form before curing, and “BCB” from DOW Corp. could be used as well for forming the same. The surface of conductive-wiring layer 41 was formed at 0 to 20 μm lower than the surface of dielectric resin layer 81. The function of the dielectric resin layer 81 for protecting the functional device 10 was superior in the case that functional device 10 had a thickness of 200 μm or less.
In
As a pretreatment for forming the seed layer 55, a desmear processing that typically uses KMnO4, NaMnO4 etc. is performed to roughen the surface of dielectric resin layer 81 and exposed surface of the electrode terminals 53, whereby the surface has a roughness of around 10 μm or less. This roughening processing increases the adhesive strength between the dielectric resin layer 81 and the seed layer 55 and conductive-wiring layer 31, thereby improving the reliability of products.
As the conductive-wiring layer 31, Cu was deposited to a thickness of 5 to 25 μm. If an inactive metal was needed, Au was used. When Cu was used for forming the wiring, electroless plating using Ni and Au was performed onto the surface to prevent oxidation of the surface, although this may be used as it is. Sn, Sn—Ag or Sn—Ag—Cu solder was provided onto the surface of the electrode wiring 3 depending on the surface mounting process by using paste printing and reflow processing. After forming the conductive-wiring layer 31, an excessive amount of seed layers 55 other than the circuit pattern is etched by a chemical etching or IBE (ion beam etching), for using the conductive-wiring layer as a circuit.
In
With reference to
With reference to
The thickness of the conductive-wiring layers 31 and 41 was 1 to 20 μm. Upon forming via-holes 61, a laser processing was performed from above. This processing formed a shape of via-holes 61 having a smaller diameter toward the bottom surface thereof and a uniform taper angle. The bottom of via-holes 61 may have sometimes a shape such that a part of the resin configuring the vias has an inner diameter increased by 10 μm due to the heating by laser. The via-plugs 74 were formed by a plating technique using conductive paste including copper and Sn—Ag based powder.
With reference to
With reference to
With reference to
With reference to
With reference to
The conductive-wiring layer 34 has the function of preventing the embedded functional device 10A from being damaged by a bending or stroking stress. Here, the conductive-wiring layer 34 can be electrically used as the ground, has the function of an electromagnetic shield, and can provide superior electric properties for the products. In particular, high-frequency electric properties at 1 GHz or above can be improved as compared to the case of absence of the conductive-wiring layer 34. The conductive-wiring layer 34, if connected to the electrode terminals 53 used as the ground of functional device 10A, can further improve the electric properties as well.
With reference to
As described above, provision of the seed layer onto the side surface, bottom portion and top portion of the vias 501 prevents internal fracture of vias, fracture of the top portion and bottom portion of vias and peel-off from the resin layer at the side surface of the vias in the event of deformation of the board, which may be caused by incorporation of the functional device in the board, to thereby provide products having a higher reliability. In particular, when a heat cycle from −55° to 125° is repeated, the board exhibits a longer lifetime as high as 2000 cycles or above, although in this case the board experiences warp of opposite directions for the higher temperature and the lower temperature. In addition, formation of the electrode terminals 53 and seed layer 511 as a common layer facilitates position observation during exposure of resist in the formation of wiring pattern of the vias 501 and electrode terminals 53, thereby providing a superior positioning accuracy. Thus, the product yield can be improved. Further, use of the filled vias increases the via area in contact with the conductive-wiring layer 31 as compared to the case of using the conformal-type ones, thereby reducing the electric resistance and improving the higher-speed electric property.
With reference to
Thus, internal fracture of the vias, fracture oldie top portion and bottom portion of the vias and peel-off of the side surface of vias from the resin layer can be prevented in the event of deformation of the board, which may be caused by incorporation of the functional device 10 in the board, similarly to the example shown in
With reference to
As a result, a portion of the internal conductor of vias 503 having a larger inner diameter and disposed near the conductive-wiring layer 31 has a larger crystal-grain diameter and a significant extending property, whereby it is possible to alleviate the stress in the event of deformation of the board, such as warp, that may be caused by incorporation of the functional device 10. On the other hand, a portion of the internal conductor of vias 503 having a smaller inner diameter and thus a smaller contact area and disposed near the conductive-wiring layer 73 scarcely extends, and yet has a superior bonding strength with respect to the conductive-wiring layer 73. Therefore, even without forming the seed layer at the interface between the side surface of vias and the conductive-wiring layer 73, disconnection of the vias can be prevented by alleviating the stress applied to the interface, thereby improving the reliability of products.
With reference to
In
In this way, the pileus structure portion of the mushroom-shaped posts 510 extends as a wedge within the dielectric resin layer in a horizontal direction (direction normal to the thickness direction) of the dielectric resin layer, thereby increasing the strength in the thickness direction between the vias and the dielectric resin in the event of thickness-wise deformation or warping stress generated in the functional-device-embedded board, even without forming the seed layer on the side surface of the vias, thereby preventing disconnection at the vias. Thus, reliability of products can be improved. On the other hand, if the vias have an ordinary trapezoid section, and if there is no increased adhesion strength between the side surface of vias and the dielectric resin layer, unlike the present exemplary embodiment, there is a possibility that a peel-off of the via conductor from the dielectric resin layer in contact therewith occurs. Note that the structure of
With reference to
The supporting substrate 71 may be preferably comprised of a single material such as Si, glass, aluminum, stainless steel, polyimide, epoxy etc., or a composite material thereof, without limitation thereto. If the supporting substrate 71 is comprised of a nonconductive material, the conductive-wiring layer 72 may be formed thereon by providing a plating seed metal thereto by sputtering or electroless plating. If the supporting substrate 71 is to be removed by a process other than the etching, a technique for providing a releasing material in advance within the material of the supporting substrate 71 may be preferably used, without limitation thereto. For example, as a releasing layer adhered onto the board comprised of a single material such as Si, glass, aluminum, stainless steel, polyimide and epoxy, ultra-thin copper-foil series, “Micro Thin (MT)” from Mitsui Mining and Smelting Co., Ltd. may be preferably used, whereas as the supporting substrate 71, “PTFE tape” from Sumitomo 3M, Inc. may be preferably used. However, the supporting substrate 71 comprised of a composite material is not limited thereto.
The pattern of conductive-wiring layer 73 comprised of copper is then formed to a thickness of 5 to 20 μm by a plating technique, without peeling-off the plating resist or after peeling-off the plating resist and forming a pattern of another plating resist. At this stage, the pattern of conductive-wiring layer 73 preferably exists on the pattern of conductive-wiring layer 72. Since the pattern of conductive-wiring layer 73 remains after the removal of supporting substrate 71, gold, copper, nickel etc. May be used therefor.
In a subsequent step, a 10- to 725-μm-thick functional device 10 is mounted, while applying heat and pressure, on the pattern of conductive-wiring layer 73 with an intervention of a 10- to 30-μm-thick adhesive layer 25 comprised of an organic resin, as shown in
In a subsequent step, as shown in
In a subsequent step, as shown in
After forming the via-holes 67 in the dielectric resin layer 86, a desmear processing is performed to remove the resin residues within the via-holes 67, and at this stage, the resin residues etc. comprised of polished particles and existing on the exposed portion of the electrode terminals 53 can also be removed at the same time. The surface of dielectric resin layer 86 has thereon concave-convex portions of 10-μm height or smaller caused by the desmear processing, providing the advantage of increasing the adhesive strength after forming the conductive-wiring layer 31 due to an anchor effect. After cleaning the conductor wiring by using a weak acid, such as dilute sulfuric acid, an electroless plating using copper, nickel etc., is performed to obtain a seed layer for the subsequent plating process. Instead, a sputtering processing may be performed to form at least one conductor layer including at least one species of element, comprised of a combination of Ti layer and Cu layer, combination of Pd layer and Cu layer, or combination of Cr layer and Cu layer. The elements configuring the seed layer were selected for achieving an efficient proceeding of the process for forming resistors, inductors, and capacitors, which are shown in
In a subsequent step, as shown in
The height of conductive-wiring layer 73 comprised of copper at this stage is about 0.5 to 20 μm lower than that of the dielectric resin layer 84 surrounding the periphery thereof. The height of conductive-wiring layers 72 and 73, which are originally formed on the supporting substrate 71, is uniform and thus can be suitably used as the electrode terminals by which the surface mounting is performed in the semiconductor device or BGA package, achieving a higher connection reliability. The circuit board thus obtained can be used in this state; however, a 5- to 30-μm-thick solder resist layer having therein arbitrary openings may be formed thereon to be used for multi-device surface mounting.
It is possible to use the state of
With reference to
In a subsequent step, as shown in
The intermediate layer 24 comprised of SUS340 was effective to prevent a warp and improve the rigidity when the board had a smaller thickness. This intermediate layer 24 was subjected to a chemical etching to have therein openings having a size larger than the outer shape of vias at arbitrary positions and to have an opening having a size equal to or larger than the outer shape of the functional device 10, because a laser processing was performed in the subsequent steps for forming vias that connect together the conductive-wiring layer 73 and the conductive-wiring layer 31. In a subsequent step, as shown in
In a subsequent step, as shown in
Upon performing the buff-polishing or grinding after plating the inside of via-holes 67, it is efficient to perform the same simultaneously with the grinding or buff-polishing the electrode terminals 53 in
The subsequent process is similar to that of
With reference to
In a subsequent step, as shown in
As compared to the case where a plurality of functional devices with different species are configured as a single circuit board, the configuration wherein a plurality of circuit boards each embedding therein a single functional device are stacked one on another has the advantage that each circuit board can be electrically tested at an intermediate stage to improve the product yield, although the overall volume is increased.
With reference to
In a further alternative, as shown in
Thereafter, bonding of the upper board and the lower of the present invention at the dielectric portion with an intervention of the adhesive layer was performed simultaneously with the conductive connection through the vias 45 by using a vacuum press, followed by a subsequent step of removing the supporting substrate, if it remains, by etching or polishing, to thereby obtain the circuit board wherein layers including the functional device are stacked one on another in a vertical direction, as shown in
The adhesive layer 40 may also be obtained by forming 30- to 500-μm-diameter via-holes by using a laser processing or 80- to 500-μm-diameter via-holes by using a drill, in a state of the adhesive layer 40 where a 25- to 38-μm-thick protective film, such as PET (polyethylene terephthalate) and PEN (polyethylenenaphthalate), is bonded onto both the surfaces thereof, and thereafter performing printing with the solder paste or conductive paste by using the protective film as a mask to fill the via-holes, and removing the protective film. In addition, the printing may be performed, without using the protective film, while using a metal mask or screen mask, such as made of stainless steel and nickel.
The adhesive layer 40 may be provided in advance onto one of the functional-device-embedded circuit boards by using a laminating technique, thereafter forming via-holes on the conductive-wiring layer by using laser etc., and performing a printing process using the protective film, metal mask or screen mask. Removal of the protective film allows the adhesive layer 40 to bond together the two circuit boards by a subsequent vacuum pressing in the present invention. The circuit boards may be used in this state, or may be used for subsequent multi-device mounting after forming a 5- to 40-μm-thick solder resist layer. In addition, using the state of
Two functional-device-embedded circuit boards of the present invention, as shown in
Note that the functional-device-embedded circuit board 203 of the present invention can be connected to a multi-layered circuit board 208 with an intervention of the adhesive layer 40 and vias 45 filled with solder paste or conductive paste, as shown in
With reference to
Since the conductive-wiring layer is directly connected from the electrode terminals 53 of the embedded functional device 10, a semi-additive technique that is capable of providing a finer circuit pattern was used to form the circuit boards 410. However, if it is possible to use a subtractive technique that provides a lower cost and a less finer circuit pattern, in a wiring processing for a 500 mm×600 mm large-sized board 411, a fabrication process performed on two separate sites is efficient in the work, to thereby improve the mass-productivity and achieve a higher product yield and a lower cost.
With reference to
Thereafter, in the process of
Here, in the step shown in
With reference to
Thereafter, in the step of
Here, in the step shown in
With reference to
Here, the AD process achieves deposition of a thickness up to several millimeters within a shorter period of time as compared to the plating. Thus, the AD process can significantly reduce the fabrication time length, and allows the inside of conductor in a portion of the vias 503 having a smaller inner diameter and disposed near the conductive-wiring layer 153 to have a finer metallic structure with smaller Cu crystal grains, and allows the inside of conductor in a portion of the vias 503 having a larger inner diameter and disposed near the conductive-wiring layer 31 to have larger Cu crystal grains compared to the portion near the wiring layer 153, thereby improving the reliability of products. Further, since an intensive energy is added to the bottom of vias 503, it is possible to obtain a superior bonding strength at the bottom of vias to thereby improve the reliability.
With reference to
In the step shown in
Since the mushroom-shaped posts 510 are formed in advance to be embedded within the resin irrespective of any techniques employed, the post portion embedded within the resin can be observed more clearly than the conductive-wiring layer 73 during the later laser processing for forming the via-holes. This provides a superior recognition of position with a higher accuracy, to raise the yield of products. In addition, presence of the pileus structure portion on the mushroom-shaped posts 510 provides a higher strength and a higher reliability as described before. Further, the smaller height of vias formed by laser processing reduces the aspect ratio of vias, thereby facilitating removal of residues at the bottom of vias during patterning of resist, and since the plating liquid in the plating bath had a higher fluidity at the bottom of vias, a reliable conductive-wiring layer 31 could be obtained.
In one exemplary embodiment of the present invention, a plurality of functional devices are connected together with a shorter distance therebetween, thereby achieving a superior high-speed electric performance. Another object of the present invention is to allow the functional-device-embedded board to be used as a circuit board having superior electric properties as well as a package due to inclusion of narrow-pitch interconnections of the top and bottom surfaces that are connected together by vias.
One embodiment of the present invention is to manufacture a highly-integrated functional-device-embedded circuit board due to three-dimensional integration of the functional devices. Another object of the present invention is to allow the conductive-wiring layer of the front and rear surfaces of the circuit board to have a uniform height and be located within the same plane, thereby improving the connection reliability between the circuit board and the electronic device.
One embodiment of the present invention is to achieve a manufacturing process having a higher reliability, even for the case of a thin and fragile functional device, without a damage thereon occurring during the fabrication stages. Another object of the present invention is to alleviate the stress caused by a difference in the thermal coefficient of expansion between the functional device and the material of the heat sink to thereby achieve a higher reliability. Another object of the present invention is to prevent a crack within the dielectric resin, conductive wiring and functional device that may result from a stress occurring in the thickness direction and board-surface direction depending on the thermal coefficient of expansion between the functional device and the peripheral dielectric resin layer in the functional-device-embedded circuit board and the area of the conductive-wiring layers formed on the front and rear surfaces, and to prevent peel-off at the interface between at least two members of the dielectric resin, conductive wiring and functional device, thereby achieving a higher reliability. Another object of the present invention is to improve the positional accuracy of the functional device and intra-board conductive wiring, raise the product yield, form a higher-specification wiring layer and reduce the size of circuit board.
One exemplary embodiment of the present invention is to planarize the conductive wiring disposed on the front and rear surfaces of the circuit board and the dielectric layer.
One exemplary embodiment of the present invention is to provide three-dimensional connection between a plurality of functional devices with a shorter distance therebetween, thereby achieving a superior high-speed electric performance. For inducing the heat radiation from the functional device, the first conductive-wiring layer may be configured as a heat-radiating patterned interconnection, which may be arbitrarily designed to alleviate the stress occurring due to the difference in the thermal coefficient of expansion between the wiring material of the board and the functional device, to achieve a higher reliability of the products. Since the outer shape of the functional-device-embedded board is larger than the outer shape of the functional device, the wiring rule of the electrode terminals of the functional device can be expanded at the front and rear surfaces thereof, thereby achieving a superior workability and reliable mounting during connection between the circuit board and the functional device.
In a preferred embodiment of the first aspect of the circuit board of the present invention, patterned interconnections in the second wiring layers and the surface of the electrode terminals are connected together with an intervention of a seed layer. The adhesive strength between the patterned interconnections of the second wiring layer and the electrode terminal is improved to thereby improve the reliability of the products. It is preferable that seed layer include at least one element selected from the group consisting of Ti, W, Cr, Pt, Au, Cu, Ni, Ag, Sn and Pd.
In a preferred embodiment of the first aspect of the circuit board the present invention, a third dielectric layer intervenes at least a part of a gap between the second dielectric layer and the second conductive-wiring layer. The adhesive strength between the second dielectric layer and the second conductive-wiring layer can be increased.
In a preferred embodiment of the first aspect of the circuit board the present invention, conductor vias that connect together patterned interconnections of the first conductive-wiring layer and patterned interconnections of the second conductive-wiring layer have a larger cross-sectional area at a portion in a vicinity of the second conductive-wiring layer than at a portion in a vicinity of the first conductive-wiring layer. In the step of metal-plating the inside of via-holes that receives therein conductor vias, observation of plating part is facilitated, and thus judgment between a superior plated state and a defective portion is facilitated, to improve the quality of products.
In a preferred embodiment of the first aspect of the circuit of the present invention, a configuration may be employed wherein the seed layer covers a side of the conductor vias that connect together the first conductive-wiring layer and the second conductive-wiring layer, and is formed between the conductor vias and the first conductive-wiring layer. For example, the conductor vias disposed near the side surface of the functional device and connecting together the first conductive-wiring layer and the second conductive-wiring layer are provided with the seed layer at the bottom portion, side surface and top portion of the conductor vias. As a result, after the functional device is embedded within the board, the seed layer that is formed against the deformation caused by the stress occurring in the thickness direction of the board due to the difference in the thermal coefficient of expansion between the functional device and the surrounding dielectric resin layer as well as the difference existing in the thickness or area between the first conductive-wiring layer and the second conductive-wiring layer increases the adhesive strength with respect to the surrounding resin and prevents peel-off at the interface with respect to the resin. In addition, the seed layer formed between the bottom portion of conductor vias and the first conductive-wiring layer and/or between the top portion of vias and the second conductive wiring layer as well as the side surface of the vias maintains a larger adhesive strength. Thus, it is possible to prevent a disconnection or a crack within the dielectric resin in the event of a deformation such as a warp, thereby achieving a higher reliability of products.
In the first aspect of the circuit board of the present invention, a configuration may be employed wherein the seed layer is formed between time conductor vias and the second conductive-wiring layer.
In the first aspect of the circuit board of the present invention, a configuration may be employed wherein a resin layer is embedded in a central surface portion of the conductor vias in a vicinity of the second conductive-wiring layer. In this case, it is possible to allow the thermal coefficient of expansion of conductor vias to be close to that of the dielectric resin layer existing outside the conductor vias, thereby improving the reliability.
In the first aspect of the circuit board of the present invention, a configuration may be employed wherein the conductor vias each include a conductor post including a uniform-diameter portion and a larger-diameter portion having a lager diameter than the uniform-diameter portion, and a via-plug formed on the conductor post, and the seed layer is formed between the via-plug and the second conductive-wiring layer. For example, the vias connecting together the first conductive-wiring layer and the second conductive-wiring layer and located near the side of the embedded functional device may include a pileus portion of a mushroom shape in the middle portion of vias, and the pileus portion may extend in the horizontal direction as a wedge toward the inside of the dielectric resin layer, thereby increasing the adhesive strength in the thickness direction between the conductor vias and the dielectric resin layer in the event of deformation and stress of warp occurring in the functional-device-embedded board even without forming the seed layer on the side surface of the vias. Thus, it is possible to prevent a disconnection in the vias, and to thereby provide a higher reliability for the products. On the other hand, for conductor vias having a trapezoidal cross-sectional shape, there is a possibility that peel-off at the interface between the side surface of vias anti the dielectric resin may occur unless reinforcement of the adhesive strength between the side surface of vias and the dielectric resin layer is provided by the seed layer.
In the first aspect of the circuit board of the present invention, a configuration may be employed wherein the conductor vias have crystal grains larger at a portion in a vicinity of the first conductive-wiring layer than at a portion in a vicinity of the second conductive-wiring layer. For example, the conductor vias may be such that a fine metal structure having smaller crystal grains is formed at a smaller-diameter portion of the conductor vias near the first conductive-wiring layer, the crystal grains are larger at a larger-diameter portion near the second conductive-wiring layer compared to the portion near the first conductive-wiring layer, and the seed layer is formed at least between the second conductive-wiring layer and the conductor vias. In this case, the size of crystal grains exerts an influence on the hardness of the structure or expansion of the alloy configuring the conductor vias. Thus, a smaller-diameter portion near the first conductive-wiring layer has a larger strength and a higher hardness. In addition, the larger-diameter portion near the second conductive-wiring layer has larger crystal grains and an expansion property, thereby alleviating the stress in the event of deformation of the board, such as a warp, occurring due to incorporation of the functional device. Therefore, the stress applied onto the interface can be alleviated even without forming the seed layer on the interface between the side surface of the conductor vias and the dielectric resin layer, thereby preventing a disconnection at the vias to improve the reliability of products.
In the first aspect of the circuit board of the present invention, a configuration may be employed wherein a part of the patterned interconnections in the second conductive-wiring layer includes one or a plurality of element selected from the group consisting of Cu, W, Cr, Pt, Ni, Zn, Fe, Al, C, Mn, Ir, Ti, N and O. In addition, a configuration may be employed wherein a part of the patterned interconnections in the second conductive-wiring layer includes one or a plurality of elements selected from the group consisting of Mg, Mn, Ti, Sr, Ba, Ca, Zn, Al, Ta, Si, Au, Zr, Nb, Hf, Pb, Bi, N and O. Further, a configuration may be employed wherein a part of patterned interconnections in the second conductive-wiring layer configures an inductor that has a spiral shape or meander shape. It is possible to reduce the volume of the passive elements embedded or surface-mounted in the board, and to obtain superior electric properties.
The first aspect of circuit board of the present invention may further include, inside of the circuit board, an intermediate conductive-wiring layer including at least one species of element selected from Fe, Ni, Cr, Co, Cu, Sn, Si and Al. The intermediate conductive-wiring layer can increase the strength of the circuit board. Use of the intermediate conductive-wiring layer as a grounding layer achieves superior electric properties. Further, the intermediate conductive-wiring layer can increase the heat radiation capability of the circuit board.
The first aspect of the circuit board of the present invention may further include a plurality of species of dielectric resin layers within the circuit board. Provision of the separate dielectric resin layers allows use of a combination of a soft resin and a hard resin, combination of a higher heat-resistant resin and a lower heat-resistant resin or combination of an expensive resin and an inexpensive resin, thereby achieving a lower cost as well as improvement of reliability of products.
In the first aspect of the circuit board of the present invention, a configuration may be employed at least one of the first and second conductive-wiring layers includes a plurality of the conductor layers, and a combination of conductor layers connected together by a conductor via that connects together the conductor layer of the first conductive-wiring layer and the conductor layer of second conductive-wiring layers include a plurality of combinations. In addition, the second conductive-wiring layer may include a plurality of the conductor layers, and one of the conductor layers of the second conductive-wiring layer that is connected to the first conductive-wiring layer by a conductor via is farther than the electrode terminals of the functional device. Further, at least one of the first and second conductive-wiring layers may include three conductor layers or more, and one of the conductor layers is connected by a conductor via to another of the conductor layers other than the other of the conductor layers nearest to the one of the conductor layers.
The first aspect of the circuit board of the present invention may further embed therein an electronic part. In the first aspect of the circuit board of the present invention, the circuit board may embed therein a plurality of functional devices that are arranged in at least one of directions parallel to a thickness direction and a board-surface direction. It is possible to reduce the line length between these functional devices, thereby achieving a circuit board having a higher-speed electric property. In addition, employment of combination of radio elements and logic and/or memory devices may achieve a multi-function circuit board. Since the functional device is not exposed on the surface, workability during the conveyance can be improved.
If the circuit board embeds therein a plurality of functional devices that are arranged in at least one of directions parallel to a thickness direction and a board-surface direction, it is preferable that adjacent two of the functional devices arranged parallel to the thickness direction of the circuit board be arranged such that the electrode terminals of one of the adjacent two oppose the electrode terminals of the other. For example, after an LSI is subjected to flip-chip bonding, the distances of LSI measured from both the functional devices are made equal to each other, thereby improving the connection reliability. In this case, a conductive paste or lead-free solder paste including at least one species of element selected from the group consisting of Sn, Ag, Cu, Bi, Zn and Pb may connect together the electrode terminals of the one of the adjacent two and the electrode terminals of the other, and may connect together one of the conductive-wiring layer connected to the one of the adjacent two and another of the conductive-wiring layer connected to the other.
In the first aspect of the circuit board of the present invention, the electrode terminals of the functional device may be connected to one of the conductive-wiring layers in the circuit board by a conductive paste or lead-free solder paste including at least one species of element selected from the group consisting of Sn, Ag, Cu, Bi, Zn and Pb.
In a preferred embodiment of the present invention, a solder resist layer having therein an opening is formed on a surface of the second conductive-wiring layer. It is possible to prevent a short-circuit failure caused by reflow of lead-free solder or melting of solder balls upon mounting another functional device.
In accordance with the first aspect of the circuit-board manufacturing method of the present invention, it is possible to perform in succession the processings of forming the first conductive-wiring layer, mounting the functional device, and forming the conductive-wiring layer, to thereby reduce the cost. By forming the first conductive-wiring layer on the supporting substrate, and mounting the functional device thereon, application of pressure during the mounting does not deform the supporting substrate to prevent bending of the functional device, to thereby prevent damage on the functional device itself. Removal of the supporting substrate to expose the first conductive-wiring layer on the rear surface of the board allows the surface of the first conductive-wiring layer to be formed on the same plane as or lower than the surface of the dielectric resin layer, whereby the surface of the dielectric resin layer plays a roll of the solder resist to obviate forming of the solder resist layer. The height of the conductive-wiring layer formed on the supporting substrate is uniform, to achieve a higher connection reliability during mounting a semiconductor device etc.
In the first aspect of the circuit-board manufacturing method of the present invention, the covering step may include the step of simultaneously covering a metal layer including at least one species of element selected from the group consisting of Fe, Ni, Cr, Co, Cu, Sn, Si and Al.
A preferred embodiment of the first aspect of the circuit-board manufacturing method of the present invention further includes the step of forming a seed layer including at least one species of element selected from the group consisting of Ti, W, Cr, Pt, Au, Cu, Ni, Ag, Sn and Pd prior to the step of funning the conductive-wiring layer, and the step of patterning the seed layer subsequent to the step of forming the conductive-wiring layer.
A preferred embodiment of the first aspect of the circuit-board manufacturing method of the present invention further includes the steps of forming a releasing layer on the supporting substrate, prior to the step of forming the first conductive-wiring layer.
In the first aspect of the circuit-board manufacturing method of the present invention, the supporting substrate may include at least one species of element selected from the group consisting of copper, iron, nickel, chromium, aluminum, titanium, silicon, nitrogen, oxygen and carbon.
In a preferred embodiment of the first aspect of the circuit-board manufacturing method oldie present invention, the step of forming the conductive-wiring layer includes the steps of consecutively forming the first and second conductor layers, and, subsequent to the step of removing the supporting substrate, removing the first conductor layer to expose the second conductor layer.
The first aspect of the circuit-board manufacturing method of the present invention may further include, subsequent to the step of forming the first conductor layer, the steps of embedding the functional-device-embedded circuit board in another supporting substrate, and forming another conductive-wiring layer on the another substrate.
The first aspect of the circuit-board manufacturing method of the present invention may further include the step of connecting a terminal of an electronic part to the conductive-wiring layer by using solder including at least one species of element selected from the group consisting of Sn, Ag, Cu, Bi, Zn and Pb.
The first aspect of the circuit-board manufacturing method of the present invention may further include, prior to the step of forming removing the supporting substrate, the steps of forming a via-hole to reach the supporting substrate from the conductive-wiring layer, and plating an inside of the via-hole.
A configuration may be employed wherein the first aspect of the circuit-board manufacturing method of the present invention further includes, prior to the step of forming the conductive-wiring layer, the step of forming a via-hole to reach the supporting substrate from the surface of the dielectric resin layer, and plating an inside of the via-hole.
A configuration may be employed wherein the first aspect of the circuit-board manufacturing method of the present invention further includes the step of filling the plated via-hole with a conductor by using an AD (aerosol deposition) technique. For example, conductor particles are bonded using an A/D technique onto the inside of via-holes located on the side of the area wherein the functional device is embedded, to thereby form conductor vias. In this ease, the functional device is embedded in the dielectric resin layer, followed by forming via-holes by using laser, removing the residues of dielectric resin at the bottom portion by using desmear processing, and thereafter depositing metal particulates, such as Cu, Au and Ni, in a vacuum ambient by using the AD process. Here, the AD process can deposit a thicker film as compared to the plating. Thus, the fabrication time length can be drastically reduced, and a fine metal structure having smaller crystal grains is formed within a smaller-inner-diameter portion of the conductor of vias near the first conductive-wiring layer, whereas larger crystal grains are formed in the larger-inner-diameter portion near the second conductive-wiring layer as compared to the portion near the first conductive-wiring layer. This improves the reliability of products.
The first aspect of the circuit-board manufacturing method of the present invention may further include, prior to the step of removing the part of the dielectric resin layer, the steps of forming a via-hole in the dielectric resin layer, forming a seed layer on a bottom portion, a side surface and a top portion of the via-hole and the surface of the dielectric resin layer, forming a conductor via by plating an inside of the via-hole, and grinding the electrode terminals of the functional device and a top surface of the conductor via. For example, via-holes penetrating from the first dielectric layer that isolates patterned interconnections of the outermost layer of the first conductive-wiring layers from one another to the second dielectric layer that isolates the electrode terminals of the functional device from one another are formed in the dielectric resin layer by laser irradiation prior to forming the second dielectric resin layer. Thereafter, the seed layer is formed on the bottom portion, side surface and top portion of the via-holes and the surface of the dielectric resin layer, followed by plating onto the entire surface without forming resist thereby Cu-plating the surface of board and the inside of via-holes and form conductor vias. Subsequently, the top surface of vias and the electrode terminals of the embedded functional device are grinded at the same time. Thereafter, the top surface of the conductor vias and the electrode terminals of the functional device are connected together after forming the seed layer. Thus, the seed layer is formed on the bottom portion, side surface and top portion of vias. As a result, the conductor vias have a strong adhesive property at the interface with respect to the resin and the overlying interconnections, against the stress in the thickness direction that is caused, as one of factors, by incorporation of the functional device in the board, thereby achieving a superior reliability of products. Note that vias may be ones referred to as filled vias wherein a plating metal is embedded, are not limited thereto, and may be ones referred to as conformal vias obtained by metal-plating only the bottom portion and side surface of vias and filling the central portion thereof with resin after the plating. If laser vias are formed in a dielectric resin layer having a thickness equivalent to or larger than that of an ordinary functional device, the aspect ratio (height/inner diameter) of vias is large. If the exposure and development is performed in this structure after applying a resist for a patterned plating, it is difficult to remove residues of the plating resist existing on the bottom portion of vias, whereby the plated state of the bottom portion has a poor reliability. On the other hand, in the manufacturing method of the present invention, the resist is not used because of plating the entire surface for the purpose of plating the inside of vias, to thereby improve the reliability.
In the first aspect of the circuit-board manufacturing method of the present invention, a configuration may be employed wherein the step of forming the conductor vias uses an entire-area plating, printing, or AD process.
In the first aspect of the circuit-board manufacturing method of the method of the present invention, a configuration may be employed wherein the method further includes the step of prior to the step of mounting the functional device, forming a conductor post on the first conductive-wiring layer; and subsequent to the step of covering the functional device, forming a via-hole in a portion of the dielectric resin layer covering the conductor post, and forming a via-plug connecting to the conductor post within the via-hole. For example, mushroom-shaped plating posts (conductor post) are formed at the location wherein the conductor vias are to be formed near the side of functional device on the first conductive-wiring layer obtained by plating onto the supporting substrate before mounting the functional device, followed by mounting the functional device to be embedded within the dielectric resin layer, and forming via-holes by laser irradiation onto the top portion of the conductor posts embedded within the dielectric resin layer. Thereafter, it is possible to perform electroless plating and subsequent electrolytic plating, or stacking plating layers within the via-holes by supplying power from the supporting substrate, to form via-plugs connected to the conductor posts, whereby the conductor vias connecting together the first conductive-wiring layer and the second conductive-wiring layer are formed. In this case, formation of the conductor posts in advance allows a portion of the conductor posts embedded within the dielectric resin layer to be observed more clearly than the first conductive-wiring layer upon later laser irradiation for forming the via-holes. Thus, a superior accuracy can be obtained in recognition of the position, to thereby improve the product yield. The pileus portion formed on the conductor posts increases the strength and improves the reliability as described before.
In the second aspect of the circuit-board manufacturing method of the present invention, at least one of two functional-device boards may be a functional-device board that is prior to removal of the supporting substrate, and the method may further include the step of removing the supporting substrate that is not removed. In addition, the conductive paste or lead-flee solder paste may include at least one species of element selected from the group consisting of Sn, Ag, Cu, Bi, Zn and Pb.
In the third aspect of the circuit-board manufacturing method of the present invention, the conductive paste or lead-free solder paste may include at least one species of element selected from the group consisting of Sn, Ag, Cu, Bi, Zn and Pb.
In the circuit-board manufacturing method of the present invention, at least one of the first conductive-wiring layer and the conductive-wiring layer may be covered by a solder resist layer having therein an opening.
A semiconductor device, SAW filter or thin-film functional device etc. formed and wired on Si, GaAs, LiTaO3, LiNbO3, quartz etc., a chip part such as condenser, resistor, inductor etc., and a device wired on a printed circuit board and flexible substrate may be preferably used as the functional device in the present invention, which is not limited thereto. Silicon, glass, ceramics, such as alumina, glass ceramics, titanium nitride and aluminum nitride, metal such as copper, stainless steel, iron, and nickel or organic resin such as thick polyimide may be used for the supporting substrate, which is not limited thereto.
The types of vias used in the present invention include, if plating conductor metal, such as gold, silver, copper and nickel is to be used, conformal vias obtained by forming via-holes in a dielectric resin layer by using laser, desmear processing using chemical liquid for removing resin residues within the vias, and subsequently forming a seed layer by using electroless plating or evaporation of Ti, W, Cr, Pt, Au, Cu, Ni, Ag, Sn, and filled vias obtained by entirely filling the inside of via-holes with plating metal, which are preferably used without limitation. The technique for forming the via-holes may preferably use UV-YAG and CO2 laser etc., without limitation thereto. The technique for exposing the electrode terminals from the dielectric resin layer may be such that a releasing layer is provided in advance on the electrode terminals upon incorporation of the functional device, and the releasing layer is removed by peel-off after curing the resin, or the resin embedding therein the functional device is cured and then grinding is performed to expose the internal electrode terminals on the board surface. Use of photosensitive type for the dielectric resin layer allows the via-holes to be formed by exposure and development.
A portion of the conductive-wiring layer exposed on the surface in the present invention may be preferably formed by performing electroless plating, electrolytic plating, printing treatment or reflow, even if the conductive-wiring layer is formed by, for example, copper plating, such as copper, nickel, gold, silver, Sn—Ag solder. However, the material of surface of the conductive-wiring layer surface is not limited thereto.
The electrode terminals formed on the functional device in the present invention may be ones referred to as cylindrical posts comprised of copper, nickel, gold, silver etc., or ball-like ones such as Sn—Ag solder, which are preferably used, without limitation thereto.
The outermost surface of the circuit board of the present invention may be preferably provided with a solder resist layer including therein openings at the desired positions in order for restricting a portion of the conductive-wiring layer from being exposed on the surface, preventing oxidation of interconnections, and preventing a short-circuit failure between the conductive-wiring layers during mounting using solder. A portion of the conductive-wiring layer exposed from the openings is subjected to an electroless plating, electrolytic plating, or printing treatment using copper, nickel, gold, silver and Sn—Ag solder, thereby forming a conductive-wiring layer having a superior oxidation resistance or a superior wettability with respect to solder.
Note that an electronic part obtained by dicing the circuit board of the present invention into a plurality of pieces and embedding the piece in another circuit board or functional device, and a board further embedding therein the circuit board fall within the scope of the claims of the present invention.
While the invention has been particularly shown and described with reference to exemplary embodiment thereof, the invention is not limited to these embodiments and modifications. As will be apparent to those of ordinary skill in the art, various changes may be made in the invention without departing from the spirit and scope of the invention as defined in the appended claims.
This application is based upon and claims the benefit of priority from Japanese patent applications No. 2007-93083 filed on Mar. 30, 2007 and No. 2008-2159 filed on Jan. 9, 2008, the disclosure of which is embedded herein in its entirety by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-093083 | Mar 2007 | JP | national |
| 2008-002159 | Jan 2008 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/056199 | 3/28/2008 | WO | 00 | 9/28/2009 |
