Patent Grant
8420520
1. Field of the Invention
The present invention relates to a method for fabricating a package. More particularly, the present invention relates to a method for fabricating a chip package.
2. Brief Description of the Related Art
Gold electroplating technology has been widely used in microelectronics and micro systems, such as in the connection between a flat panel display and a driver chip. A driver chip can be connected to a flat panel display with a TCP (tape carrier package) or COG (Chip-On-Glass) method, which is mainly implemented with an electroplating technology for gold bumps. Thereby, the dimension of a driver chip can be greatly reduced, and the space is effectively saved. Besides, the electroplating process has the advantage of low cost. Therefore, the gold-bump electroplating technology has vitally prospered in the related fields.
In the Au-electroplating technology, the electroplating solution usually contains cyamide because of the reliability and technical maturity of cyamide-containing electroplating solutions. However, cyamide is a lethal poison. Therefore, the factory and the wastewater processing facility have to meet the required standards lest the personnel be harmed and the environment be polluted.
Anyhow, with the popularization of eco-awareness, a cyamide-free Au-electroplating solution has become an important topic.
The primary objective of the present invention is to provide a method for fabricating chip package, wherein a 1X stepper is used to expose a photoresist layer with at least two of G-line, H-line and I-line, and a gold layer is electroplated over a passivation layer with an electroplating solution containing Au and sulfite ion.
In order to reach the above objectives, a method for fabricating chip package comprises the following steps: providing a circuit structure over a semiconductor substrate and a passivation layer over the circuit structure, an opening in the passivation layer exposing a pad of the circuit structure; forming a metal layer on the pad and over the passivation layer; forming a photoresist layer on the metal layer, an opening in the photoresist layer exposing the metal layer, wherein said forming the photoresist layer comprises exposing the photoresist layer using 1X stepper with at least two of G-line, H-line and I-line; electroplating a gold layer over the metal layer exposed by the opening in the photoresist layer with an electroplating solution containing gold and sulfite ion; removing the photoresist layer and the metal layer not under the gold layer; dicing the semiconductor substrate into a plurality of chips; and packaging the chips.
To enable the objectives, technical contents, characteristics and accomplishments of the present invention, the embodiments of the present invention are to be described in detail in cooperation with the attached drawings below.
Each of structures disclosed in the present invention is constructed over a semiconductor substrate or over a semiconductor wafer. After the structural construction of the polymer layer 38, 50 or 64 or of the metal bump 78 over the semiconductor substrate or over the semiconductor wafer, described in the following paragraphs, the semiconductor substrate or the semiconductor wafer is diced into a plurality of chips. Next, the chips can be packaged with a wire-bonding technology, a TAB (Tape Automated Bonding) technology or an ACF (Anisotropic Conductive Film) technology.
Referring to
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The passivation layer 8 is commonly made of silicon oxide (such as SiO2), PSG (phosphosilicate glass), silicon nitride (such as Si3N4), or silicon oxynitride. The passivation layer 8 commonly has a thickness of more than 0.35 μm. In a preferred case, the silicon nitride layer in the passivation layer 8 has a thickness of more than 0.3 μm. Ten methods for depositing the passivation layer 8 are described as below.
In a first method, the passivation layer 8 is formed by depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm using a CVD method and then depositing a silicon nitride layer with a thickness of 0.2 and 1.2 μm on the silicon oxide layer using a CVD method.
In a second method, the passivation layer 8 is formed by depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm using a CVD method, next depositing a silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm on the silicon oxide layer using a Plasma Enhanced CVD (PECVD) method, and then depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the silicon oxynitride layer using a CVD method.
In a third method, the passivation layer 8 is formed by depositing a silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm using a CVD method, next depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the silicon oxynitride layer using a CVD method, and then depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the silicon oxide layer using a CVD method.
In a fourth method, the passivation layer 8 is formed by depositing a first silicon oxide layer with a thickness of between 0.2 and 0.5 μm using a CVD method, next depositing a second silicon oxide layer with a thickness of between 0.5 and 1 μm on the first silicon oxide layer using a spin-coating method, next depositing a third silicon oxide layer with a thickness of between 0.2 and 0.5 μm on the second silicon oxide layer using a CVD method, and then depositing a silicon nitride layer with a thickness of 0.2 and 1.2 μm on the third silicon oxide using a CVD method.
In a fifth method, the passivation layer 8 is formed by depositing a silicon oxide layer with a thickness of between 0.5 and 2 μm using a High Density Plasma CVD (HDP-CVD) method and then depositing a silicon nitride layer with a thickness of 0.2 and 1.2 μm on the silicon oxide layer using a CVD method.
In a sixth method, the passivation layer 8 is formed by depositing an Undoped Silicate Glass (USG) layer with a thickness of between 0.2 and 3 μm, next depositing an insulating layer of TEOS, PSG or BPSG (borophosphosilicate glass) with a thickness of between 0.5 and 3 μm on the USG layer, and then depositing a silicon nitride layer with a thickness of 0.2 and 1.2 μm on the insulating layer using a CVD method.
In a seventh method, the passivation layer 8 is formed by optionally depositing a first silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm using a CVD method, next depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the first silicon oxynitride layer using a CVD method, next optionally depositing a second silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm on the silicon oxide layer using a CVD method, next depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the second silicon oxynitride layer or on the silicon oxide using a CVD method, next optionally depositing a third silicon oxynitride layer with a thickness of between 0.05 and 0.15 μm on the silicon nitride layer using a CVD method, and then depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the third silicon oxynitride layer or on the silicon nitride layer using a CVD method.
In a eighth method, the passivation layer 8 is formed by depositing a first silicon oxide layer with a thickness of between 0.2 and 1.2 μm using a CVD method, next depositing a second silicon oxide layer with a thickness of between 0.5 and 1 μm on the first silicon oxide layer using a spin-coating method, next depositing a third silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the second silicon oxide layer using a CVD method, next depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the third silicon oxide layer using a CVD method, and then depositing a fourth silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the silicon nitride layer using a CVD method.
In a ninth method, the passivation layer 8 is formed by depositing a first silicon oxide layer with a thickness of between 0.5 and 2 μm using a HDP-CVD method, next depositing a silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the first silicon oxide layer using a CVD method, and then depositing a second silicon oxide layer with a thickness of between 0.5 and 2 μm on the silicon nitride using a HDP-CVD method.
In a tenth method, the passivation layer 8 is formed by depositing a first silicon nitride layer with a thickness of between 0.2 and 1.2 μm using a CVD method, next depositing a silicon oxide layer with a thickness of between 0.2 and 1.2 μm on the first silicon nitride layer using a CVD method, and then depositing a second silicon nitride layer with a thickness of between 0.2 and 1.2 μm on the silicon oxide layer using a CVD method.
Referring to
The opening 8a have a maximum transverse dimension of between 2 and 30 μm or between 30 and 300 μm. The shape of the opening 8a may be a circle, and the diameter of the circle-shaped opening 8a may be between 2 and 30 μm or between 30 and 300 μm. Alternatively, the shape of the opening 8a may be a square, and the greatest diagonal length of the square-shaped opening 8a may be between 2 and 30 μm or between 30 and 300 μm. Alternatively, the shape of the opening 8a may be a polygon, and the polygon-shaped opening 8a may have a greatest diagonal length of between 3 and 30 μm or between 30 and 300 μm. Alternatively, the shape of the opening 8a may also be a rectangle, and the rectangle-shaped opening 8a may have a width of between 2 and 40 μm. Further, there may be the semiconductor device 4 under the pad 12 exposed by the opening 8a. Alternatively, there may be none of the semiconductor device 4 under the pad 12 exposed by the opening 8a.
Referring to
The semiconductor substrate 2, the circuit structure 6, the dielectric layer 10, the passivation layer 8 and the pad 12 are described in the above paragraphs. Below, the element of integrated circuit 22 under the passivation layer 8 may be any of the structures shown in
Embodiment 1
Referring to
The material of the polymer layer 24 may include polyimide (PI), benzocyclobutane (BCB), polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer, or a porous dielectric material. The polymer layer 24 has a thickness t1 of between 2 and 30 μm. In a preferred case, the polymer layer 24 has a thickness t1 of between 3 and 12 μm.
The polymer layer 24 can be formed by a spin-on coating process, a process for thermally pressing a dry film on the passivation layer 8, or a screen-printing process. Below, the process of forming a patterned polymer layer 24 is exemplified with the case of spin-on coating a polyimide layer on the passivation layer 8 and then patterning the polyimide layer. Alternatively, the polymer layer 24 can be formed by spin-on coating a layer of benzocyclobutane, polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer or a porous dielectric material on the passivation layer 8, and then patterning the layer.
In a first method, the polymer layer 24 can be formed by spin-on coating a positive-type photosensitive polyimide layer having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the passivation layer 8, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, then curing or heating the developed polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, and then removing the residual polymeric material or other contaminants on the upper surface of the pads 12 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with at least two openings in the polyimide layer exposing two pads 12, respectively.
In a second method, the polymer layer 24 can be formed by spin-on coating a first positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the passivation layer 8, then baking the spin-on coated first polyimide layer, then exposing the baked first polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked first polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked first polyimide layer, then developing the exposed first polyimide layer, then curing or heating the developed first polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured first polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then optionally removing the residual polymeric material or other contaminants on the upper surface of the pads 12 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the first polyimide layer can be patterned with at least two first openings in the first polyimide layer exposing two pads 12, respectively, then spin-on coating a second positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the first polyimide layer and on the pads 12, then baking the spin-on coated second polyimide layer, then exposing the baked second polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked second polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked second polyimide layer, then developing the exposed second polyimide layer, then curing or heating the developed second polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured second polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then removing the residual polymeric material or other contaminants on the upper surface of the pads 12 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the second polyimide layer can be patterned with at least two second openings in the second polyimide layer exposing two pads 12, respectively. Alternatively, to lead the polymer layer 24 with a relatively great thickness, forming the polymer layer 24 may further comprise forming one or more other polyimide layers on the second polyimide layer, following the steps of forming the first or second polyimide layer. The step of removing the residual polymeric material or other contaminants on the upper surface of the pads 12 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen can be only performed after the topmost polyimide layer of the polymer layer 24 has been cured.
Referring to
Next, a seed layer 28 having a thickness of 500 and 2,000 angstroms, and preferably between 750 and 1,500 angstroms, is formed on the adhesion/barrier layer 26. The seed layer 28 may be formed by a sputtering method, a vapor deposition method, an electroless plating method or a PVD (Physical Vapor Deposition) method. The seed layer 28 is beneficial to electroplating a metal layer thereon. Thus, the material of the seed layer 28 varies with the material of the electroplated metal layer formed on the seed layer 28. When a gold layer is to be electroplated on the seed layer 28, gold is a preferable material to the seed layer 28.
For example, when the adhesion/barrier layer 26 is formed by sputtering a titanium-containing layer with a thickness of between 2,000 and 5,000 angstroms, and preferably between 2,500 and 3,500 angstroms, the seed layer 28 can be formed by sputtering a gold layer with a thickness of between 500 and 2,000 angstroms, and preferably between 750 and 1,500 angstroms, on the titanium-containing layer. When the adhesion/barrier layer 26 is formed by sputtering a titanium layer with a thickness of between 2,000 and 5,000 angstroms, and preferably between 2,500 and 3,500 angstroms, the seed layer 28 can be formed by sputtering a gold layer with a thickness of between 500 and 2,000 angstroms, and preferably between 750 and 1,500 angstroms, on the titanium layer. When the adhesion/barrier layer 26 is formed by sputtering a layer of titanium-tungsten alloy with a thickness of between 2,000 and 5,000 angstroms, and preferably between 2,500 and 3,500 angstroms, the seed layer 28 can be formed by sputtering a gold layer with a thickness of between 500 and 2,000 angstroms, and preferably between 750 and 1,500 angstroms, on the layer of titanium-tungsten alloy.
Referring to
The photoresist layer 30 can be formed by spin-on coating a positive-type photosensitive polymer layer having a thickness of between 5 and 30 μm, and preferably of between 7 and 15 μm, on the seed layer 28, then exposing the photosensitive polymer layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the photosensitive polymer layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the photosensitive polymer layer, then developing the exposed polymer layer, and then removing the residual polymeric material or other contaminants on the seed layer 28 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the photoresist layer 30 can be patterned with at least two openings 30a and 30b in the photoresist layer 30 exposing the seed layer 28.
Referring to
Thereby, the gold layer 32 can be electroplated in a short time with an enough thickness of between 3 and 18 μm, and preferably between 3 and 8 μm, for example, on the seed layer 28 made of gold that has been formed on the adhesion/barrier layer 26 made of titanium or titanium-tungsten alloy.
Referring to
Thereafter, referring to
Thereby, in the present invention, at least one metal trace 34 can be formed on the polymer layer 24 and on the pad 12. Alternatively, at least one metal pad 36 can be formed on the pad 12. Either of the metal trace 34 and the metal pad 36 can be formed of the adhesion/barrier layer 26, the seed layer 28 on the adhesion/barrier layer 26 and the electroplated gold layer 32 on the seed layer 28. Besides, the metal trace 34 may be a RDL (Re-Distribution Layer). Alternatively, the metal trace 34 may comprises a coil serving as an inductor.
Besides, the pitch between the neighboring metal traces 34 may be greater than 3 microns or may range from 3 microns to 500 microns, from 3 microns to 200 microns, from 3 microns to 100 microns, from 3 microns to 50 microns, from 3 microns to 20 microns or from 3 microns to 10 microns. The metal trace 34 may have a width of between 1 micron and 500 microns, of between 1 micron and 200 microns, of between 1 micron and 100 microns, of between 1 micron and 50 microns, of between 1 micron and 20 microns or of between 1 micron and 10 microns, and preferably of between 2 microns and 20 microns. The spacing between the neighboring metal traces 34 may be greater than 1 micron or may range from 1 micron to 500 microns, from 1 micron to 200 microns, from 1 micron to 100 microns, from 1 micron to 50 microns, from 1 micron to 20 microns or from 1 micron to 10 microns, and preferably from between 2 microns to 20 microns.
Referring to
The polymer layer 38 can be formed via a spin-on coating process, a process for thermally pressing a dry film, or a screen-printing process. Below, the process of forming a patterned polymer layer 38 is exemplified with the case of spin-on coating a polyimide layer on the polymer layer 24 and on the gold layer 32, and then patterning the polyimide layer. Alternatively, the polymer layer 38 can be formed by spin-on coating a layer of benzocyclobutane, polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer or a porous dielectric material, and then patterning the layer.
In a first method, the polymer layer 38 can be formed by spin-on coating a positive-type photosensitive polyimide layer having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the polymer layer 24 and on the gold layer 32, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, then curing or heating the developed polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, and then removing the residual polymeric material or other contaminants on the upper surface of the gold layer 32 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with at least two openings in the polyimide layer exposing the gold layer 32 of metal trace 34 and the gold layer 32 of the metal pad 36, respectively.
In a second method, the polymer layer 38 can be formed by spin-on coating a first positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the polymer layer 24 and on the gold layer 32, then baking the spin-on coated first polyimide layer, then exposing the baked first polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked first polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked first polyimide layer, then developing the exposed first polyimide layer, then curing or heating the developed first polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured first polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then optionally removing the residual polymeric material or other contaminants on the upper surface of the gold layer 32 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the first polyimide layer can be patterned with at least two first openings in the first polyimide layer exposing the gold layer 32 of metal trace 34 and the gold layer 32 of the metal pad 36, respectively, then spin-on coating a second positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the first polyimide layer and on the gold layer 32 exposed by the first openings in the first polyimide layer, then baking the spin-on coated second polyimide layer, then exposing the baked second polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked second polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked second polyimide layer, then developing the exposed second polyimide layer, then curing or heating the developed second polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured second polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then removing the residual polymeric material or other contaminants on the upper surface of the gold layer 32 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the second polyimide layer can be patterned with at least two second openings in the second polyimide layer exposing the gold layer 32 of the metal trace 34 and the gold layer 32 of the metal pad 36, respectively. Alternatively, to lead the polymer layer 38 with a relatively great thickness, forming the polymer layer 38 may further comprise forming one or more other polyimide layers on the second polyimide layer, following the steps of forming the first or second polyimide layer. The step of removing the residual polymeric material or other contaminants on the upper surface of the gold layer 32 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen can be only performed after the topmost polyimide layer of the polymer layer 38 has been cured.
Besides, from a top perspective view, the position of the gold layer 32 of the metal trace 34 exposed by the opening 38a is different from that of the pad 12 the metal trace 34 is connected to.
Below, the description is based on the case that the polymer layer 38 has been formed on the gold layer 32 and the polymer layer 24. Alternatively, there may be no polymer layer 38 on the gold layer 32 and the polymer layer 24.
After the above-mentioned processes have been completed, the semiconductor substrate 2 can be diced into a plurality of individual semiconductor chips. Referring to
In the present invention, the strength of bonding the wire 42 to the gold layer 32 of the metal trace 34 exposed by the opening 38a of a chip or to the gold layer 32 of the metal pad 36 exposed by the opening 38b of a chip may ranges from 100 to 1000 mN, from 200 to 1000 mN, or from 200 to 500 mN. After the wire-bonding process shown in
Referring to
Embodiment 2
Referring to
The photoresist layer 30 can be formed by spin-on coating a positive-type photosensitive polymer layer having a thickness of between 5 and 30 μm, and preferably of between 7 and 15 μm, on the seed layer 28, then exposing the photosensitive polymer layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the photosensitive polymer layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the photosensitive polymer layer, then developing the exposed polymer layer, and then removing the residual polymeric material or other contaminants on the seed layer 28 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the photoresist layer 30 can be patterned with the opening 30c in the photoresist layer 30 exposing the seed layer 28.
Referring to
Thereby, the gold layer 46 can be electroplated in a short time with an enough thickness of between 3 and 18 μm, and preferably between 3 and 8 μm, for example, on the seed layer 28 made of gold that has been formed on the adhesion/barrier layer 26 made of titanium or titanium-tungsten alloy.
Referring to
Thereafter, referring to
Thereby, in the present invention, at least one interconnecting metal trace 48 can be formed on the polymer layer 24 and on the pads 12, connecting the pads 12. The interconnecting metal trace 48 can be formed of the adhesion/barrier layer 26, the seed layer 28 on the adhesion/barrier layer 26 and the electroplated gold layer 46 on the seed layer 28.
Besides, the pitch between the neighboring metal interconnection traces 48 may be greater than 3 microns or may range from 3 microns to 500 microns, from 3 microns to 200 microns, from 3 microns to 100 microns, from 3 microns to 50 microns, from 3 microns to 20 microns or from 3 microns to 10 microns. The interconnecting metal trace 48 may have a width of between 1 micron and 500 microns, of between 1 micron and 200 microns, of between 1 micron and 100 microns, of between 1 micron and 50 microns, of between 1 micron and 20 microns or of between 1 micron and 10 microns, and preferably of between 2 microns and 20 microns. The spacing between the neighboring metal interconnection traces 48 may be greater than 1 micron or may range from 1 micron to 500 microns, from 1 micron to 200 microns, from 1 micron to 100 microns, from 1 micron to 50 microns, from 1 micron to 20 microns or from 1 micron to 10 microns, and preferably from between 2 microns to 20 microns.
Referring to
The material of the polymer layer 50 may include polyimide, benzocyclobutane, polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer, or a porous dielectric material. The polymer layer 50 has a thickness of between 2 and 30 μm. In a preferred case, the polymer layer 50 has a thickness of between 3 and 12 μm. The polymer layer 50 can be formed via a spin-on coating process, a process for thermally pressing a dry film, or a screen-printing process. Below, the process of forming a patterned polymer layer 50 is exemplified with the case of spin-on coating a polyimide layer on the polymer layer 24 and on the gold layer 46, and then patterning the polyimide layer. Alternatively, the polymer layer 50 can be formed by spin-on coating a layer of benzocyclobutane, polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer or a porous dielectric material, and then patterning the layer.
In a first method, the polymer layer 50 can be formed by spin-on coating a positive-type photosensitive polyimide layer having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the polymer layer 24 and on the gold layer 46, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, then curing or heating the developed polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, and then removing the residual polymeric material or other contaminants on the upper surface of the gold layer 46 or the pad 12 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with at least one opening in the polyimide layer exposing the gold layer 46 of interconnecting metal trace 48, the pad 12, or the gold layer 46 over the pad 12.
In a second method, the polymer layer 50 can be formed by spin-on coating a first positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the polymer layer 24 and on the gold layer 46, then baking the spin-on coated first polyimide layer, then exposing the baked first polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked first polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked first polyimide layer, then developing the exposed first polyimide layer, then curing or heating the developed first polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured first polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then optionally removing the residual polymeric material or other contaminants on the upper surface of the gold layer 46 or the pad 12 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the first polyimide layer can be patterned with at least one first opening in the first polyimide layer exposing the gold layer 46 of interconnecting metal trace 48, the pad 12, or the gold layer 46 over the pad 12, then spin-on coating a second positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the first polyimide layer and on the gold layer 46 and/or the pad 12 exposed by the first opening in the first polyimide layer, then baking the spin-on coated second polyimide layer, then exposing the baked second polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked second polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked second polyimide layer, then developing the exposed second polyimide layer, then curing or heating the developed second polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured second polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then removing the residual polymeric material or other contaminants on the upper surface of the gold layer 46 or the pad 12 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the second polyimide layer can be patterned with at least one second opening in the second polyimide layer exposing the gold layer 46 of interconnecting metal trace 48, the pad 12, or the gold layer 46 over the pad 12. Alternatively, to lead the polymer layer 50 with a relatively great thickness, forming the polymer layer 50 may further comprise forming one or more other polyimide layers on the second polyimide layer, following the steps of forming the first or second polyimide layer. The step of removing the residual polymeric material or other contaminants on the upper surface of the gold layer 46 or the pad 12 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen can be only performed after the topmost polyimide layer of the polymer layer 50 has been cured.
Below, the description is based on the case that the polymer layer 50 has been formed on the gold layer 46 and the polymer layer 24. Alternatively, there may be no polymer layer 50 on the gold layer 46 and the polymer layer 24. After the above-mentioned processes have been completed, the semiconductor substrate 2 can be diced into a plurality of individual semiconductor chips.
Referring to
Embodiment 3
Referring to
Referring to
Referring to
The photoresist layer 30 can be formed by spin-on coating a positive-type photosensitive polymer layer having a thickness of between 5 and 30 μm, and preferably of between 7 and 15 μm, on the seed layer 28, then exposing the photosensitive polymer layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 438 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the photosensitive polymer layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the photosensitive polymer layer, then developing the exposed polymer layer, and then removing the residual polymeric material or other contaminants on the seed layer 28 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the photoresist layer 30 can be patterned with at least one opening 30a in the photoresist layer 30 exposing the seed layer 28.
Referring to
Thereby, the gold layer 56 can be electroplated in a short time with an enough thickness of between 3 and 18 μm, and preferably between 3 and 8 μm, for example, on the seed layer 28 made of gold that has been formed on the adhesion/barrier layer 26 made of titanium or titanium-tungsten alloy.
Referring to
Referring to
Next, a gold bump 60 having a thickness of between 2 and 15 μm or between 8 and 30 μm, can be electroplated on the gold layer 56 exposed by the opening 58a with an electroplating solution containing gold of between 1 and 20 grams per litter (g/l), and preferably between 5 and 15 g/l, and sulfite ion of 10 and 120 g/l, and preferably between 30 and 90 g/l. The electroplating solution may further comprise sodium ion, to be turned into a solution of gold sodium sulfite (Na3Au(SO3)2), or may further comprise ammonium ion, to be turned into a solution of gold ammonium sulfite ((NH4)3[Au(SO3)2]). The operational parameters of electroplating the gold bump 60 are described below:
Referring to
Thereafter, referring to
Referring to
Referring to
The pitch between the neighboring metal traces 62 may be greater than 3 microns or may range from 3 microns to 500 microns, from 3 microns to 200 microns, from 3 microns to 100 microns, from 3 microns to 50 microns, from 3 microns to 20 microns or from 3 microns to 10 microns. The metal trace 62 may have a width of between 1 micron and 500 microns, of between 1 micron and 200 microns, of between 1 micron and 100 microns, of between 1 micron and 50 microns, of between 1 micron and 20 microns or of between 1 micron and 10 microns, and preferably of between 2 microns and 20 microns. The spacing between the neighboring metal traces 62 may be greater than 1 micron or may range from 1 micron to 500 microns, from 1 micron to 200 microns, from 1 micron to 100 microns, from 1 micron to 50 microns, from 1 micron to 20 microns or from 1 micron to 10 microns, and preferably from between 2 microns to 20 microns.
Referring to
The polymer layer 64 can be formed via a spin-on coating process, a process for thermally pressing a dry film, or a screen-printing process. Below, the process of forming a patterned polymer layer 64 is exemplified with the case of spin-on coating a polyimide layer on the polymer layer 24, on the gold layer 56 and on the gold bump 60, and then patterning the polyimide layer. Alternatively, the polymer layer 64 can be formed by spin-on coating a layer of benzocyclobutane, polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer or a porous dielectric material, and then patterning the layer.
In a first method, the polymer layer 64 can be formed by spin-on coating a positive-type photosensitive polyimide layer having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the polymer layer 24, on the gold layer 56 and on the gold bump 60, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 464 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, then curing or heating the developed polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, and then removing the residual polymeric material or other contaminants on the upper surface of the gold bump 60 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with at least one opening in the polyimide layer exposing the gold bump 60.
In a second method, the polymer layer 64 can be formed by spin-on coating a first positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the polymer layer 24, on the gold layer 56 and on the gold bump 60, then baking the spin-on coated first polyimide layer, then exposing the baked first polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 464 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked first polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked first polyimide layer, then developing the exposed first polyimide layer, then curing or heating the developed first polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured first polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then optionally removing the residual polymeric material or other contaminants on the upper surface of the gold bump 60 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the first polyimide layer can be patterned with at least one first opening in the first polyimide layer exposing the gold bump 60, then spin-on coating a second positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the first polyimide layer and on the gold bump 60 exposed by the first opening in the first polyimide layer, then baking the spin-on coated second polyimide layer, then exposing the baked second polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 464 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked second polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked second polyimide layer, then developing the exposed second polyimide layer, then curing or heating the developed second polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured second polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then removing the residual polymeric material or other contaminants on the upper surface of the gold bump 60 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the second polyimide layer can be patterned with at least one second opening in the second polyimide layer exposing the gold bump 60. Alternatively, to lead the polymer layer 64 with a relatively great thickness, forming the polymer layer 64 may further comprise forming one or more other polyimide layers on the second polyimide layer, following the steps of forming the first or second polyimide layer. The step of removing the residual polymeric material or other contaminants on the upper surface of the gold bump 60 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen can be only performed after the topmost polyimide layer of the polymer layer 64 has been cured.
Below, the description is based on the case that the polymer layer 64 has been formed on the gold layer 56 and the polymer layer 24. Alternatively, there may be no polymer layer 64 on the gold layer 56 and the polymer layer 24. After the above-mentioned processes have been completed, the semiconductor substrate 2 can be diced into a plurality of individual semiconductor chips.
Referring to
Embodiment 4
Referring to
Referring to
The polymer layer 70 can be formed via a spin-on coating process, a process for thermally pressing a dry film, or a screen-printing process. Below, the process of forming a patterned polymer layer 70 is exemplified with the case of spin-on coating a polyimide layer on the polymer layer 24 and on the gold layer 56, and then patterning the polyimide layer. Alternatively, the polymer layer 70 can be formed by spin-on coating a layer of benzocyclobutane, polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer or a porous dielectric material, and then patterning the layer.
In a first method, the polymer layer 70 can be formed by spin-on coating a positive-type photosensitive polyimide layer having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the polymer layer 24 and on the gold layer 56, then baking the spin-on coated polyimide layer, then exposing the baked polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 470 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked polyimide layer, then developing the exposed polyimide layer, then curing or heating the developed polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, and then removing the residual polymeric material or other contaminants on the upper surface of the gold layer 56 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the polyimide layer can be patterned with at least one opening in the polyimide layer exposing the gold layer 56.
In a second method, the polymer layer 70 can be formed by spin-on coating a first positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the polymer layer 24 and on the gold layer 56, then baking the spin-on coated first polyimide layer, then exposing the baked first polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 470 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked first polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked first polyimide layer, then developing the exposed first polyimide layer, then curing or heating the developed first polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured first polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then optionally removing the residual polymeric material or other contaminants on the upper surface of the gold layer 56 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the first polyimide layer can be patterned with at least one first opening in the first polyimide layer exposing the gold layer 56, then spin-on coating a second positive-type polyimide layer with photosensitivity having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the first polyimide layer and on the gold layer 56 exposed by the first opening in the first polyimide layer, then baking the spin-on coated second polyimide layer, then exposing the baked second polyimide layer using a 1X stepper with at least two of G-line having a wavelength ranging from 434 to 470 nm, H-line having a wavelength ranging from 403 to 407 nm, and I-line having a wavelength ranging from 363 to 367 nm, illuminating the baked second polyimide layer, that is, G-line and H-line, G-line and I-line, H-line and I-line, or G-line, H-line and I-line illuminate the baked second polyimide layer, then developing the exposed second polyimide layer, then curing or heating the developed second polyimide layer at a peak temperature of between 200 and 290° C., between 290 and 330° C. or between 330 and 400° C. for a time of between 30 minutes and 2 hours in a nitrogen ambient or in an oxygen-free ambient, the cured second polyimide layer having a thickness of between 2 and 30 μm, and preferably between 3 and 12 μm, then removing the residual polymeric material or other contaminants on the upper surface of the gold layer 56 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen, such that the second polyimide layer can be patterned with at least one second opening in the second polyimide layer exposing the gold layer 56. Alternatively, to lead the polymer layer 70 with a relatively great thickness, forming the polymer layer 70 may further comprise forming one or more other polyimide layers on the second polyimide layer, following the steps of forming the first or second polyimide layer. The step of removing the residual polymeric material or other contaminants on the upper surface of the gold layer 56 with an O2 plasma or a plasma containing fluorine of below 200 PPM and oxygen can be only performed after the topmost polyimide layer of the polymer layer 70 has been cured.
Referring to
Next, a seed layer 74 having a thickness of 500 and 2,000 angstroms, and preferably between 750 and 1,500 angstroms, is formed on the adhesion/barrier layer 72. The seed layer 74 may be formed by a sputtering method, a vapor deposition method, an electroless plating method or a PVD (Physical Vapor Deposition) method. The seed layer 74 is beneficial to electroplating a metal layer thereon. Thus, the material of the seed layer 74 varies with the material of the electroplated metal layer formed on the seed layer 74. When a gold layer is to be electroplated on the seed layer 74, gold is a preferable material to the seed layer 74.
For example, when the adhesion/barrier layer 72 is formed by sputtering a titanium-containing layer with a thickness of between 2,000 and 5,000 angstroms, and preferably between 2,500 and 3,500 angstroms, the seed layer 74 can be formed by sputtering a gold layer with a thickness of between 500 and 2,000 angstroms, and preferably between 750 and 1,500 angstroms, on the titanium-containing layer. When the adhesion/barrier layer 72 is formed by sputtering a titanium layer with a thickness of between 2,000 and 5,000 angstroms, and preferably between 2,500 and 3,500 angstroms, the seed layer 74 can be formed by sputtering a gold layer with a thickness of between 500 and 2,000 angstroms, and preferably between 750 and 1,500 angstroms, on the titanium layer. When the adhesion/barrier layer 72 is formed by sputtering a layer of titanium-tungsten alloy with a thickness of between 2,000 and 5,000 angstroms, and preferably between 2,500 and 3,500 angstroms, the seed layer 74 can be formed by sputtering a gold layer with a thickness of between 500 and 2,000 angstroms, and preferably between 750 and 1,500 angstroms, on the layer of titanium-tungsten alloy.
Referring to
Referring to
Thereby, the gold bump 78 can be electroplated in a short time with an enough thickness of between 2 and 15 μm or between 8 and 30 μm, for example, on the seed layer 74 made of gold that has been formed on the adhesion/barrier layer 72 made of titanium or titanium-tungsten alloy.
Referring to
Thereafter, referring to
Thereby, in the present invention, the gold bump 78 having a thickness of between 2 and 15 μm or between 8 and 30 μm can be formed over the gold layer 56 of the metal trace 62 exposed by the opening 70a. The gold bump 78 may have a wire (such as a gold wire) bonded thereon by a wire-bonding process, may have a tape bonded thereon using a tape automated bonding (TAB) technology, may be bonded with a flexible film, or may be bonded with a wire (such as an ITO (Indium-Tin-Oxide)-containing wire or a gold-containing wire) of a rigid circuit board using an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). The rigid circuit board may be a glass substrate, a ceramic substrate, or an organic substrate (such as a printed circuit board).
After the above-mentioned processes have been completed, the semiconductor substrate 2 can be diced into a plurality of individual semiconductor chips. Referring to
The gold bump 60 or 78 as shown in the third or fourth embodiment can be bonded with a wire bond, a tape, a gold layer or tin layer of a ceramic substrate or printed circuit board, a gold layer or indium-tin-oxide layer of a glass substrate, or a tin layer or gold layer of a flexible film. The following description is related to packaging the semiconductor chip shown in
Referring to
Referring to
The above-mentioned tape 86 is formed by thermally pressing a copper foil onto an adhesive layer 89 on a first polymer layer 88, such as polyimide, then patterning the copper foil using a photolithography and etching processes to form a patterned copper trace 92, next forming a solder mask 90 on the patterned copper trace 92 by spin-on coating a second polymer layer on the patterned copper trace 92 and on the adhesive layer 89, and then patterning the second polymer layer using a photolithography process to have some portion of the patterned copper trace 92 exposed to be joined with the gold bump 60, or by screen-printing a second polymer layer on part of the patterned copper trace 92 and on the adhesive layer 89, and next electroless plating a tin layer 94 on the exposed patterned copper trace 92 to be joined with the gold bump 60 of the third embodiment or with the gold bump 78 of the fourth embodiment.
Alternatively, the above-mentioned tape 86 is formed by thermally pressing a patterned copper trace 92 on an adhesive layer 89 on a first polymer layer 88, such as polyimide, next screen-printing a solder mask 90 on part of the patterned copper trace 92 and on the adhesive layer 89, having some portion of the patterned copper trace 92 exposed, and next electroless plating a tin layer 94 on the exposed patterned copper trace 92 to be joined with the gold bump 60 of the third embodiment or with the gold bump 78 of the fourth embodiment.
Referring to
Alternatively, instead of the tin layer 94, the inner lead may include a gold layer electroless plated on the inner part of the patterned copper trace 92 to connect the inner lead of the tape 86 to the gold bump 60 or 78 of the third or fourth embodiment.
When the tin layer 94 is formed on the inner part of the copper trace 92, the inner lead of the tape 86 may be bonded to the gold bump 60 or 78 of the third or fourth embodiment using a thermal pressing process. In the thermal pressing process, a tin-gold alloy 96 is formed between the gold bump 60 or 78 of the third or fourth embodiment and the inner part of the copper trace 92.
When, instead of the tin layer 94, a gold layer is formed on the inner part of the copper trace 92, the inner lead of the tape 86 may be bonded to the gold bump 60 or 78 of the third or fourth embodiment using a thermal pressing process. In the thermal pressing process, the gold layer on the inner part of the copper trace 92 is bonded to the gold bump 60 or 78 of the third or fourth embodiment via a gold-to-gold eutectic bonding.
Further, after the process of bonding the tape 86 to the gold bump 60 or 78 of the third or fourth embodiment, a polymeric material 98, such as polyimide, is formed to enclose the inner leads of the tape 86 and the gold bump 60 or 78 of the third or fourth embodiment.
In one embodiment, a side of the outer leads of the tape 86 may be connected to a glass substrate via ACF (Anisotropic Conductive Film) or ACP (Anisotropic Conductive Paste). The other side of the outer leads of the tape 86 may be connected to a printed circuit board via the tin-to-gold bonding, tin-to-tin bonding or gold-to-gold bonding using a thermal press process. Alternatively, a side of the outer leads of the tape 86 is connected to a glass substrate via ACF or ACP, and the other part of the outer leads of the tape 86 is also connected to a printed circuit board via ACF or ACP.
Alternatively, referring to
Alternatively, referring to
Alternatively, referring to
In the process of fabricating a metal trace 128 of the flexible film 122, a metal layer, such as a layer of nickel, titanium, chromium or a titanium-tungsten alloy, is sputtered on a polymer layer 124. Next, a seed layer, such as a copper layer, is sputtered on the metal layer. Next, a photoresist layer is formed on the seed layer and an opening in the photoresist layer exposes the seed layer. Next, a copper layer is electroplated on the seed layer exposed by the opening in the photoresist layer. Next, the photoresist layer is removed, and then the seed layer and the metal layer not under the electroplated copper layer are also removed.
After the metal trace 128 is formed on the polymer layer 124, a solder mask 126 is formed on the copper layer of the metal trace 128 and on the polymer layer 124 by screen printing or laminating. An opening 126a in the solder mask 126 exposes the copper layer of the metal trace 128. For example, the solder mask 126 may be formed by laminating a polyimide layer having a thickness of between 4 and 60 μm, and preferably of between 6 and 24 μm, on the metal trace 128 and on the polymer layer 124, then removing part of the laminated polyimide layer using laser for forming the opening 126a in the laminated polyimide layer exposing the copper layer of the metal trace 128. Alternatively, the laminated polyimide layer may be photosensitive, and the opening 126a in the laminated polyimide layer may be formed by a photolithography process.
Next, via an electroless plating method, a tin layer 130 is formed on the copper layer of the metal trace 128 exposed by the opening 126a. Therefore, the flexible film 122 comprises an inner lead containing an inner part of the electroplated copper layer of the metal trace 128 and the tin layer 130 or gold layer on the inner part of the electroplated copper layer of the metal trace 128, and an outer lead containing an outer part of the electroplated copper layer of the metal trace 128. The inner lead extends to a central region of the flexible film 122, used to be bonded with the gold bump 60 of the third embodiment or to the gold bump 78 of the fourth embodiment. The outer lead extends to a peripheral region of the flexible film 122, used to be connected to a external element, such as another semiconductor chip, printed circuit board containing a core with glass fiber and multiple circuit layer over and under the core, glass substrate, flexible film containing a polymer layer, such as polyimide, having a thickness of between 30 and 200 μm and a circuit layer on the polymer layer, or ceramic substrate. The inner lead is connected to the outer lead.
Alternatively, instead of the tin layer 130, the inner lead may include a gold layer electroless plated on the inner part of the electroplated copper layer of the metal trace 128 to connect the inner lead of the flexible film 122 to the gold bump 60 or 78 of the third or fourth embodiment.
When the tin layer 130 is formed on the inner part of the electroplated copper layer of the metal trace 128, the inner lead of the metal trace 128 may be bonded to the gold bump 60 or 78 of the third or fourth embodiment using a thermal pressing process. In the thermal pressing process, a tin-gold alloy 132 is formed between the gold bump 60 or 78 of the third or fourth embodiment and the inner part of the electroplated copper layer of the metal trace 128.
When, instead of the tin layer 130, a gold layer is formed on the inner part of the copper layer of the metal trace 128, the inner lead of the flexible film 122 may be bonded to the gold bump 60 or 78 of the third or fourth embodiment using a thermal pressing process. In the thermal pressing process, the gold layer on the inner part of the copper layer of the metal trace 128 is bonded to the gold bump 60 or 78 of the third or fourth embodiment via a gold-to-gold eutectic bonding.
Further, after the process of bonding the flexible film 122 to the gold bump 60 or 78 of the third or fourth embodiment, a polymeric material 134, such as polyimide, is formed to enclose the gold bump 60 or 78 of the third or fourth embodiment.
In one embodiment, a side of the outer leads of the flexible film 122 may be connected to a glass substrate via ACF (Anisotropic Conductive Film) or ACP (Anisotropic Conductive Paste). The other side of the outer leads of the flexible film 122 may be connected to a printed circuit board via the tin-to-gold bonding, tin-to-tin bonding or gold-to-gold bonding using a thermal press process. Alternatively, a side of the outer leads of the flexible film 122 is connected to a glass substrate via ACF or ACP, and the other part of the outer leads of the flexible film 122 is also connected to a printed circuit board via ACF or ACP.
Those described above are the embodiments to exemplify the present invention to enable the person skilled in the art to understand, make and use the present invention. However, it is not intended to limit the scope of the present invention. Any equivalent modification and variation according to the spirit of the present invention is to be also included within the scope of the claims stated below.
This application claims priority to U.S. provisional application No. 60/801,067, filed on May 18, 2006, which is herein incorporated by reference in its entirety.
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