Patent Application
20120061814
The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a leadframe interposer over a semiconductor die and TSV substrate for vertical electrical interconnect.
Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
Many applications require a high level of functional integration, which can be achieved with a package-on-package (PoP).
A need exists to provide efficient stacking of semiconductor die and a vertical interconnect structure without inducing undue stress or defects in the semiconductor package. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate having a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate, mounting a first semiconductor die over the substrate, providing a leadframe having a base plate and a plurality of base leads extending from the base plate, forming an etch-resistant conductive layer over a surface of the base plate opposite the base leads, mounting the leadframe to the substrate over the first semiconductor die, depositing an encapsulant over the substrate and first semiconductor die, removing the base plate while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads, and forming an interconnect structure over a surface of the substrate opposite the base leads.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate, mounting a first semiconductor die over the substrate, providing an interposer having a base plate and a plurality of base leads extending from the base plate, forming a conductive layer over a surface of the base plate opposite the base leads, mounting the leadframe to the substrate over the first semiconductor die, depositing an encapsulant over the substrate and first semiconductor die, and removing the base plate while retaining the conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate, mounting a first semiconductor die over the substrate, providing an interposer having a base plate and a plurality of base leads extending from the base plate, mounting the leadframe to the substrate over the first semiconductor die, depositing an encapsulant over the substrate and first semiconductor die, and removing the base plate while retaining a portion of the base plate opposite the base leads to electrically isolate the base leads.
In another embodiment, the present invention is a semiconductor device comprising a substrate and first semiconductor die mounted over the substrate. An interposer has a base plate and a plurality of base leads extending from the base plate. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining a portion of the base plate opposite the base leads to electrically isolate the base leads.
a-4c illustrate further detail of the representative semiconductor packages mounted to the PCB;
a-5c illustrate a semiconductor wafer with a plurality of semiconductor die separated by saw streets;
a-6n illustrate a process of forming a leadframe interposer over a semiconductor die and TSV substrate for vertical electrical interconnect;
a-7h illustrate a process of forming a leadframe interposer over a semiconductor die and BT laminate PCB for vertical electrical interconnect;
The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.
Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.
Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.
Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation. To singulate the die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
Electronic device 50 may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 may be a subcomponent of a larger system. For example, electronic device 50 may be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. The miniaturization and the weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.
In
In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
For the purpose of illustration, several types of first level packaging, including wire bond package 56 and flip chip 58, are shown on PCB 52. Additionally, several types of second level packaging, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package (DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, and quad flat package 72, are shown mounted on PCB 52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
a-4c show exemplary semiconductor packages.
b illustrates further detail of BCC 62 mounted on PCB 52. Semiconductor die 88 is mounted over carrier 90 using an underfill or epoxy-resin adhesive material 92. Wire bonds 94 provide first level packaging interconnect between contact pads 96 and 98. Molding compound or encapsulant 100 is deposited over semiconductor die 88 and wire bonds 94 to provide physical support and electrical isolation for the device. Contact pads 102 are formed over a surface of PCB 52 using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads 102 are electrically connected to one or more conductive signal traces 54 in PCB 52. Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52.
In
BGA 60 is electrically and mechanically connected to PCB 52 with a BGA style second level packaging using bumps 112. Semiconductor die 58 is electrically connected to conductive signal traces 54 in PCB 52 through bumps 110, signal lines 114, and bumps 112. A molding compound or encapsulant 116 is deposited over semiconductor die 58 and carrier 106 to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die 58 to conduction tracks on PCB 52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be mechanically and electrically connected directly to PCB 52 using flip chip style first level packaging without intermediate carrier 106.
a shows a semiconductor wafer 120 with a base substrate material 122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components 124 is formed on wafer 120 separated by saw streets 126, as described above.
b shows a cross-sectional view of a portion of semiconductor wafer 120. Each semiconductor die 124 has a back surface 128 and an active surface 130 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 130 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die 124 may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing.
An electrically conductive layer 132 is formed over active surface 130 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 132 operates as contact pads electrically connected to the circuits on active surface 130. Bumps 134 are formed over contact pads 132. In one embodiment, semiconductor die 124 is a flipchip type semiconductor die.
In
a-6n illustrate, in relation to
An electrically conductive layer 144 is formed over surface 146 and electrically conductive layer 148 is formed over surface 149 of semiconductor wafer 140 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layers 144 and 148 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layers 144 and 148 operate as contact pads for electrical interconnect. Conductive layers 144 and 148 also include redistribution layers (RDL) for routing signals across and through semiconductor wafer 140. Semiconductor wafer 140 with TSV 142 and conductive layers 144 and 148 constitute TSV wafer or substrate 150.
In
e shows a wafer-form leadframe or interposer 154 having base plate 156 with integrated base leads or conductive bodies 158 extending from the base plate.
Leading with base leads 158, leadframe 154 is aligned over conductive layer 144b to position base leads 158 around a perimeter of semiconductor die 124.
In
i shows another embodiment with encapsulant 164 deposited through optional openings 168 formed in base plate 156.
j shows an embodiment with a portion of base plate 156 over semiconductor die 124 removed by an etching process to form window 170.
In
In
TSV substrate 150 is singulated through encapsulant 164 with saw blade or laser cutting tool into individual Fo-WLCSP 176. Semiconductor die 124 is electrically connected through contact pads 132 and bumps 134 to TSV substrate 150 and base leads 158. Leadframe 154 provides a simple and cost effective structure for vertical interconnect of semiconductor die 124, as well as efficient package stacking with the vertical clearance or headroom with base leads 158. Leadframe 154 provides a balanced structure and reduces warpage. In addition, PPF conductive layer 162 serves as an etch stop when removing base plate 156 to form base leads 158.
a-7h illustrate, in relation to
An electrically conductive layer 184 is formed over surface 186 and electrically conductive layer 188 is formed over surface 190 of PCB 180 using BT laminate, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layers 184 and 188 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layers 184 and 188 operate as contact pads for electrical interconnect. Conductive layers 184 and 188 also include RDL for routing signals across and through PCB 180.
In
d shows a wafer-form leadframe or interposer 194 having base plate 196 with integrated base leads or conductive bodies 198 extending from the base plate. Leadframe 194 contains multiple rows of base leads 198, similar to
Leading with base leads 198, leadframe 194 is aligned over conductive layer 184b to position base leads 198 around a perimeter of semiconductor die 124.
In
In another embodiment, a portion of base plate 196 over semiconductor die 124 is removed by an etching process to form a window, similar to
In
In
PCB 180 is singulated through encapsulant 204 with saw blade or laser cutting tool into individual Fo-WLCSP 212. Semiconductor die 124 is electrically connected through contact pads 132 and bumps 134 to PCB 180 and base leads 198. Leadframe 194 provides a simple and cost effective structure for vertical interconnect of semiconductor die 124, as well as efficient package stacking with the vertical clearance or headroom with base leads 198. Leadframe 194 provides a balanced structure and reduces warpage. In addition, PPF conductive layer 202 serves as an etch stop when removing base plate 196 to form base leads 198.
Semiconductor die 222 is mounted active surface-to-back surface to semiconductor die 124 with b-stage coating 230, prior to mounting leadframe 154 in
Semiconductor die 242 is mounted active surface-to-back surface to semiconductor die 124 with b-stage coating 250, prior to mounting leadframe 194 in
An encapsulant or molding compound 270 is deposited over semiconductor die 262 and Fo-WLCSP 220 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 270 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 270 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
An encapsulant or molding compound 284 is deposited over semiconductor die 274 and Fo-WLCSP 220 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 284 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 284 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. A portion of encapsulant 284 is removed by an etching process to expose conductive layer 162. Bumps 286 are formed over the exposed conductive layer 162.
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
