SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Abstract

The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an example of a non-isolated DC-DC converter including a semiconductor device of an embodiment of the invention;

FIG. 2 is a waveform chart illustrating the basic operation of the non-isolated DC-DC converter in FIG. 1;

FIG. 3 is an overall plan view illustrating the main surface side of a package that forms the appearance of the semiconductor device in FIG. 1;

FIG. 4 is an overall plan view illustrating the back surface side of the package in FIG. 3;

FIG. 5 is a side view of the package in FIG. 3 and FIG. 4;

FIG. 6 is an overall plan view showing the interior of the package in FIG. 1 in a see-through manner;

FIG. 7 is a sectional view taken along line X1-X1 of FIG. 6;

FIG. 8 is a sectional view taken along line Y1-Y1 of FIG. 6;

FIG. 9 is an explanatory drawing of the internal configuration of the package in FIG. 1;

FIG. 10 is an overall plan view showing the interior of the package in FIG. 6 with metal plates removed in a see-through manner;

FIG. 11 is an overall plan view showing the interior of the package in FIG. 6 with metal plates and semiconductor chips removed in a see-through manner;

FIG. 12 is an overall plan view illustrating the uppermost layer of the semiconductor chip in FIG. 6 where a field effect transistor for high side is formed;

FIG. 13 is an overall plan view illustrating the uppermost wiring layer of the semiconductor chip in FIG. 12;

FIG. 14 is an overall plan view illustrating the gate electrode layer of the semiconductor chip in FIG. 12;

FIG. 15 is an enlarged plan view of region A of the semiconductor chip in FIG. 14;

FIG. 16 is a sectional view taken along line X2-X2 of FIG. 12;

FIG. 17 is a sectional view taken along line Y2-Y2 of FIG. 12;

FIG. 18 is an enlarged sectional view of a unit transistor cell formed in the semiconductor chip in FIG. 16;

FIG. 19 is a sectional view taken along line X3-X3 of FIG. 12, illustrating the uppermost layer and the uppermost wiring layer;

FIG. 20 is a sectional view of the uppermost layer and the uppermost wiring layer in FIG. 19 with a metal plate and a bonding wire added thereto;

FIG. 21 is an overall plan view illustrating the uppermost layer of the semiconductor chip in FIG. 6 where a field effect transistor for low side is formed;

FIG. 22 is an overall plan view showing the uppermost wiring layer of the semiconductor chip in FIG. 21;

FIG. 23 is an overall plan view showing the gate electrode layer of the semiconductor chip in FIG. 21;

FIG. 24 is an enlarged plan view of region B of the semiconductor chip in FIG. 23;

FIG. 25 is an overall plan view of a semiconductor device investigated by the present inventors;

FIG. 26 is a graph chart in which a semiconductor device in an embodiment of the invention and the semiconductor device in FIG. 25 are compared with each other for voltage conversion efficiency;

FIG. 27 is a graph chart in which a semiconductor device in an embodiment of the invention and the semiconductor device in FIG. 25 are compared with each other for loss;

FIG. 28 is an overall plan view of another semiconductor device investigated by the present inventors;

FIG. 29 is an overall plan view of another semiconductor device investigated by the present inventors;

FIG. 30 is an overall plan view of further another semiconductor device investigated by the present inventors;

FIG. 31 is a plan view of a substantial part in an example of mounting electronic components that construct a non-isolated DC-DC converter including the semiconductor device in FIG. 3;

FIG. 32 is a side view showing the non-isolated DC-DC converter in FIG. 31 as viewed from the direction indicated by arrow F;

FIG. 33 is an overall plan view showing the interior of the package of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 34 is a sectional view taken along line X5-X5 of FIG. 33;

FIG. 35 is a sectional view taken along line Y5-Y5 of FIG. 33;

FIG. 36 is an overall plan view showing the interior of the package of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 37 is a sectional view taken along line X6-X6 of FIG. 36;

FIG. 38 is a sectional view taken along line Y6-Y6 of FIG. 36;

FIG. 39 is an overall plan view showing the interior of the package of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 40 is a sectional view taken along line X7-X7 of FIG. 39;

FIG. 41 is a sectional view taken along line Y7-Y7 of FIG. 39;

FIG. 42 is an overall plan view showing the interior of the package of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 43 is a sectional view taken along line X8-X8 of FIG. 42;

FIG. 44 is a sectional view taken along line Y8-Y8 of FIG. 42;

FIG. 45 is an overall plan view of a metal plate investigated by the present inventors;

FIG. 46 is a sectional view taken along line X9-X9 of FIG. 45;

FIG. 47 is a side view showing the metal plate in FIG. 45 as viewed from the direction indicated by arrow J;

FIG. 48 is an overall plan view showing the interior of the package of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 49 is a sectional view taken along line X10-X10 of FIG. 48;

FIG. 50 is a sectional view taken along line Y10-Y10 of FIG. 48;

FIG. 51 is a side view of a substantial part of the metal plate in FIG. 48 and the like;

FIG. 52 is an overall plan view showing the interior of the package of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 53 is an overall plan view showing the interior of the package with the metal plates in FIG. 52 removed;

FIG. 54 is a sectional view taken along line X11-X11 of FIG. 52;

FIG. 55 is a sectional view taken along line Y11-Y11 of FIG. 52;

FIG. 56 is a sectional view of a substantial part of the semiconductor chip where a field effect transistor for high side is formed, of the semiconductor device in FIG. 52 in a manufacturing process;

FIG. 57 is a sectional view of the substantial part of the semiconductor chip in the manufacturing process, following FIG. 56;

FIG. 58 is a sectional view of the substantial part of the semiconductor chip in the manufacturing process, following FIG. 57;

FIG. 59 is an overall plan view showing the interior of the package of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 60 is an overall plan view showing the interior of the package of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 61 is a sectional view taken along line X13-X13 of FIG. 60;

FIG. 62 is a sectional view taken along line Y13-Y13 of FIG. 60;

FIG. 63 is an enlarged sectional view of a substantial part of a metal plate in FIG. 60;

FIG. 64 is a circuit diagram of an example of a non-isolated DC-DC converter including a semiconductor device of another embodiment of the invention;

FIG. 65 is an overall plan view showing the interior of the package of the semiconductor device in FIG. 64 in a see-through manner;

FIG. 66 is an overall plan view showing the interior of the package in FIG. 65 with metal plates removed in a see-through manner;

FIG. 67 is an overall plan view showing the uppermost layer of the semiconductor chip where a power transistor for low-side switch is formed, in the semiconductor device in FIG. 65;

FIG. 68 is an overall plan view showing the uppermost wiring layer of the semiconductor chip in FIG. 67 where a power transistor for low-side switch is formed;

FIG. 69 is an overall plan view showing the gate electrode layer of the semiconductor chip in FIG. 67 where a power transistor for low-side switch is formed;

FIG. 70 is a sectional view taken along line Y15-Y15 of FIG. 67;

FIG. 71 is an overall plan view showing the interior of the package PA of a semiconductor device of another embodiment of the invention in a see-through manner;

FIG. 72 is an overall plan view showing the interior of the package in FIG. 71 with metal plates removed in a see-through manner;

FIG. 73 is an overall plan view showing the uppermost wiring layer of semiconductor chips in the semiconductor device in FIG. 71 and FIG. 72;

FIG. 74 is an overall plan view illustrating the positional relation between the gate electrode layer of the semiconductor chips in FIG. 73 and metal plates;

FIG. 75 is an overall plan view showing the gate electrode layer of a semiconductor chip in FIG. 73;

FIG. 76 is an enlarged plan view of region K of the gate electrode layer in FIG. 75;

FIG. 77 is a flowchart of a manufacturing process for a semiconductor device of an embodiment of the invention;

FIG. 78 is a plan view of an example of a lead frame used in the manufacturing process for a semiconductor device in FIG. 77;

FIG. 79 is an enlarged plan view of a unit region in the lead frame that underwent the die bonding process for a semiconductor device in FIG. 77;

FIGS. 80A and 80B are plan views of an example of a metal plate frame used in the manufacturing process for a semiconductor device in FIG. 77;

FIG. 81 is an enlarged plan view of a unit region in a lead frame that underwent the metal plate bonding process for a semiconductor device in FIG. 77;

FIG. 82 is an enlarged plan view of a unit region in a lead frame that underwent the wire bonding process for a semiconductor device in FIG. 77;

FIG. 83 is an enlarge plan view of a unit region in a lead frame that underwent the molding process for a semiconductor device in FIG. 77;

FIG. 84 is a flowchart of a manufacturing process for a semiconductor device of another embodiment of the invention;

FIG. 85 is an enlarged plan view of one unit region in a lead frame in a manufacturing process for a semiconductor device of further another embodiment of the invention;

FIG. 86 is a sectional view taken along line X16-X16 of FIG. 85;

FIG. 87 is a sectional view taken along line Y16-Y16 of FIG. 85;

FIG. 88 is an enlarged plan view of one unit region in a lead frame in the manufacturing process for a semiconductor device, following FIG. 85;

FIG. 89 is a sectional view taken along line X17-X17 of FIG. 88;

FIG. 90 is a sectional view taken along line Y17-Y17 of FIG. 88;

FIG. 91 is an enlarged plan view of a unit region in a lead frame that underwent the wire bonding process for a semiconductor device, following FIG. 88;

FIG. 92 is an overall plan view showing the interior of the package of a semiconductor device manufactured by the manufacturing method for a semiconductor device to be described with reference to FIG. 85 to FIG. 91 in a see-through manner;

FIG. 93 is a sectional view taken along line X18-X18 of FIG. 92;

FIG. 94 is a sectional view taken along line Y18-Y18 of FIG. 92;

FIG. 95 is an overall plan view showing the interior of the package in another example of the semiconductor device in FIG. 64 in a see-through manner;

FIG. 96 is an overall plan view showing the interior of the package in FIG. 95 with metal plates removed in a see-through manner;

FIG. 97 is an overall plan view showing the uppermost layer of the semiconductor chip where a power transistor for low-side switch is formed, in the semiconductor device in FIG. 95; and

FIG. 98 is an overall plan view showing the uppermost wiring layer of the semiconductor chip in FIG. 97 where a power transistor for low-side switch is formed.

Claims

1. A semiconductor device comprising: first, second, and third chip mounting portions comprised of electric conductor;a plurality of external terminals disposed around the first, second, and third chip mounting portions;a first semiconductor chip including a first field effect transistor;a second semiconductor chip including a second field effect transistor;a third semiconductor chip including a circuit that drives the first and second field effect transistors; anda sealing body that covers part of the first, second, and third chip mounting portions, part of the external terminals, and the first, second, and third semiconductor chips,wherein the first, second, third semiconductor chips are respectively disposed over the first, second, and third chip mounting portions,wherein the external terminals include:a first power supply terminal for supplying a first power supply to the drain of the first field effect transistor; anda second power supply terminal for supplying a second power supply whose potential is lower than the first power supply to the source of the second field effect transistor,wherein there is provided a first metal plate that electrically connects the source of the first field effect transistor with the drain of the second field effect transistor,wherein there is provided a second metal plate that electrically connect the source of the second field effect transistor with the second power supply terminal,wherein the second metal plate includes a first portion, a second portion, and a third portion,wherein the first portion is connected to the source electrode over the second semiconductor chip,wherein the second portion and the third portion are so provided as to respectively connect the first portion and the second power supply terminal, andwherein the second portion and the third portion are so disposed as to respectively straddle two intersecting sides of the second semiconductor chip.

2. The semiconductor device according to claim 1, wherein the second metal plate is not disposed directly above the four corners of the second semiconductor chip.

3. The semiconductor device according to claim 1, wherein a gate electrode and a source electrode of the first field effect transistor are electrically connected to the third semiconductor chip through a first bonding wire,wherein a gate electrode and a source electrode of the second field effect transistor are electrically connected to the third semiconductor chip through a second bonding wire, andwherein the width of the first and second metal plates is larger than the diameter of the first and second bonding wires.

4. The semiconductor device according to claim 3, wherein a source electrode of the first semiconductor chip includes a first source electrode region to which the first metal plate is connected and a second source electrode region to which the first bonding wire is connected,wherein an insulating film is formed between the first source electrode region and the second source electrode region,wherein a source electrode of the second semiconductor chip includes a third source electrode region to which the second metal plate is connected and a fourth source electrode region to which the second bonding wire is connected, andwherein an insulating film is formed between the third source electrode region and the fourth source electrode region.

5. The semiconductor device according to claim 1, wherein a drain electrode of the first field effect transistor is formed over the back surface of the first semiconductor chip and is electrically connected to the first chip mounting portion, andwherein a drain electrode of the second field effect transistor is formed over the back surface of the second semiconductor chip and is electrically connected to the second chip mounting portion.

6. The semiconductor device according to claim 1, wherein the first and second semiconductor chips include a set of short sides and a set of long sides intersecting therewith, andwherein in the first and second semiconductor chips, there is disposed gate wiring along the direction of the long sides thereof.

7. The semiconductor device according to claim 6, wherein the short sides of the second metal plate intersect with the gate wiring.

8. The semiconductor device according to claim 1, wherein the area of the second semiconductor chip is larger than the area of the first semiconductor chip, and the area of the first semiconductor chip is larger than the area of the third semiconductor chip.

9. The semiconductor device according to claim 1, wherein the sum totals of the lengths of the long sides and short sides of the first semiconductor chip are respectively larger than the sum totals of the lengths of the long sides and short sides of the third semiconductor chip.

10. The semiconductor device according to claim 1, wherein the planar area of the first portion of the second metal plate is smaller than the planar area of the second semiconductor chip.

11. The semiconductor device according to claim 1, wherein the uppermost portion of the third portion of the second metal plate in the direction perpendicular to the main surface of the second semiconductor chip is positioned between the second semiconductor chip and the second power supply terminal.

12. The semiconductor device according to claim 1, wherein a cut portion of a hanging portion that connects the second metal plate to a frame, in the third portion of the second metal plate, is positioned between the second semiconductor chip and the second power supply terminal.

13. The semiconductor device according to claim 3, wherein the highest portions of the first and second metal plates in the direction perpendicular to the main surfaces of the first and second semiconductor chips are lower than the highest portions of the first and second bonding wires in the direction perpendicular to the main surfaces of the first and second semiconductor chips.

14. The semiconductor device according to claim 1, wherein the thickness of at least part of the periphery of the first portion of the second metal plate is thinner than the thickness of an internal portion of the second metal plate.

15. The semiconductor device according to claim 14, wherein the thickness of at least part of the periphery of the first portion of the second metal plate is not more than half the thickness of an internal portion of the second metal plate.

16. The semiconductor device according to claim 1, wherein a slit extended from the second external terminal to the first portion of the second metal plate is formed in the second portion and the third portion of the second metal plate.

17. The semiconductor device according to claim 1, wherein an opening is formed in the first portion of the second metal plate.

18. The semiconductor device according to claim 1, wherein a protrusion is provided to the surfaces of the first and second metal plates opposed to the first and second semiconductor chips.

19. The semiconductor device according to claim 1, wherein the first and second semiconductor chips include an epitaxial layer, and the thickness of a source electrode formed in the first and second semiconductor chips is thinner than the thickness of the epitaxial layer.

20. The semiconductor device according to claim 1, wherein a source electrode of the first and second semiconductor chips includes an electrode body whose principal material is aluminum and a metal layer for oxidation prevention positioned over the upper face of the electrode body connected with the first and second metal plates.

21. The semiconductor device according to claim 20, wherein the metal layer for oxidation prevention is formed by depositing a metal layer comprised of nickel and a metal layer comprised of gold over the upper face of the electrode body in this order.

22. The semiconductor device according to claim 1, wherein the centers of the first, second, and third semiconductor chips are disposed of f the center of the sealing body.

23. The semiconductor device according to claim 1, wherein in the first and second metal plates, there is provided a groove in faces opposed to the first and second semiconductor chips, and the grooves are extended to sides of the first and second metal plates.

24. The semiconductor device according to claim 1, wherein in proximity to sides intersecting each other of the second chip mounting portion, there is disposed a wiring portion extended in L shape along sides of the second chip mounting portion intersecting each other, at a distance from the second chip mounting portion, and the wiring portion is connected with the second power supply terminal.

25. A manufacturing method of a semiconductor device comprising the steps of: (a) preparing a lead frame integrally having in each unit region thereof first, second, and third chip mounting portions and a plurality of external terminals that are disposed around the first, second, and third chip mounting portions and include a first power supply terminal for supplying a relatively high power supply potential and a second power supply terminal for supplying a relatively low power supply potential;(b) respectively mounting first, second, and third semiconductor chips over the first, second, and third chip mounting portions of the lead frame;(c) respectively mounting first and second metal plates over electrodes of the first and second semiconductor chips;(d) after the steps (a), (b), and (c), connecting a bonding wire to an electrode of the third semiconductor chip; and(e) after the step (d), sealing part of the first, second, and third chip mounting portions, part of the external terminals, the bonding wires, and the first, second, and third semiconductor chips with a sealing body.

26. The manufacturing method of a semiconductor device according to claim 25, wherein the first metal plate electrically connects the source of a first field effect transistor formed in the first semiconductor chip with the drain of a second field effect transistor formed in the second semiconductor chip, andwherein the second metal plate electrically connects the source of the second field effect transistor formed in the second semiconductor chip with the second power supply terminal.

27. A manufacturing method of a semiconductor device comprising the steps of: (a) preparing a lead frame integrally having in each unit region thereof first, second, and third chip mounting portions and a plurality of external terminals that are disposed around the first, second, and third chip mounting portions and include a first power supply terminal for supplying a relatively high power supply potential and a second power supply terminal for supplying a relatively how power supply potential;(b) respectively mounting first, second, and third semiconductor chips over the first, second, and third chip mounting portions of the lead frame through solder;(c) respectively mounting first and second metal plates over electrodes of the first and second semiconductor chips through solder;(d) after the steps (b) and (c) applying heat to the solder to melt the solder and respectively joining the first, second, and third semiconductor chips with the first, second, and third chip mounting portions and respectively joining the first and second metal plates with electrodes of the first and second semiconductor chips;(e) after the step (d), connecting a bonding wire to an electrode of the third semiconductor chip; and(f) after the step (e), sealing part of the first, second, and third chip mounting portions, part of the external terminals, the bonding wires, and the first, second, and third semiconductor chips with a sealing body.

28. The manufacturing method of a semiconductor device according to claim 27, wherein the first metal plate electrically connects the source of a first field effect transistor formed in the first semiconductor chip with the drain of a second field effect transistor formed in the second semiconductor chip, andwherein the second metal plate electrically connects the source of a second field effect transistor formed in the second semiconductor chip with the second power supply terminal.

29. A manufacturing method of a semiconductor device comprising the steps of: (a) preparing a lead frame integrally having in each unit region thereof first, second, and third chip mounting portions and a plurality of external terminals that are disposed around the first, second, and third chip mounting portions and include a first power supply terminal for supplying a relatively high power supply potential and a second power supply terminal for supplying a relatively low power supply potential;(b) respectively mounting first, second, and third semiconductor chips over the first, second, and third chip mounting portions of the lead frame;(c) respectively mounting first and second metal plates over electrodes of the first and second semiconductor chips in a lump;(d) after the steps (a), (b), and (c), connecting a bonding wire to an electrode of the third semiconductor chip; and(e) after the step (d), sealing part of the first, second, and third chip mounting portions, part of the external terminals, the bonding wires, and the first, second, and third semiconductor chips with a sealing body.

30. A manufacturing method of a semiconductor device comprising the steps of: (a) preparing a lead frame integrally having in each unit region thereof first, second, and third chip mounting portions and a plurality of external terminals that are disposed around the first, second, and third chip mounting portions and include a first power supply terminal for supplying a relatively high power supply potential and a second power supply terminal for supplying a relatively low power supply potential;(b) respectively mounting first, second, and third semiconductor chips over the first, second, and third chip mounting portions of the lead frame;(c) respectively mounting first and second metal plates over electrodes of the first and second semiconductor chips;(d) after the steps (a), (b), and (c), mounting a third metal plate over the first metal plate and mounting fourth and fifth metal plates over the second metal plate;(e) after the step (d), connecting a bonding wire to an electrode of the third semiconductor chip; and(f) after the step (e), sealing part of the first, second, and third chip mounting portions, part of the external terminals, the bonding wires, and the first, second, and third semiconductor chips with a sealing body,wherein the third, fourth, and fifth metal plates are identical in construction.