The disclosed embodiments relate to interconnect structures formed between stacked semiconductor dies in a semiconductor die assembly. In several embodiments, the present technology relates to an interconnect structure having redundant conductive electrical connectors.
Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to external circuitry.
Within some die packages, semiconductor dies can be stacked upon and electrically connected to one another by interconnects placed between adjacent dies. The interconnects can be connected to the bond pads of adjacent dies with metal solder. One challenge with metal solder bonding, however, is that the metal solder does not always bond properly to the interconnects and/or the bond pads. As a result, the interconnects may be open circuited, which can cause the die package to not function properly. This, in turn, can reduce process yield during manufacturing.
Specific details of several embodiments of stacked semiconductor die assemblies having interconnect structures with redundant electrical connectors and associated systems and methods are described below. The terms “semiconductor device” and “semiconductor die” generally refer to a solid-state device that includes semiconductor material, such as a logic device, memory device, or other semiconductor circuit, component, etc. Also, the terms “semiconductor device” and “semiconductor die” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device. Depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. A person skilled in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer level or at the die level. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to
As used herein, the terms “vertical,” “lateral,” “upper” and “lower” can refer to relative directions or positions of features in the semiconductor die assemblies in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations.
The assembly 100 can further include a thermally conductive casing 110 (“casing 110”). The casing 110 can include a cap portion 112 and a wall portion 113 attached to or integrally formed with the cap portion 112. The cap portion 112 can be attached to the top-most first semiconductor die 102a by a first bond material 114a (e.g., an adhesive). The wall portion 113 can extend vertically away from the cap portion 112 and be attached to a peripheral portion 106 of the first semiconductor die 102a (known to those skilled in the art as a “porch” or “shelf) by a second bond material 114b (e.g., an adhesive). In addition to providing a protective covering, the casing 110 can serve as a heat spreader to absorb and dissipate thermal energy away from the semiconductor dies 102. The casing 110 can accordingly be made from a thermally conductive material, such as nickel (Ni), copper (Cu), aluminum (Al), ceramic materials with high thermal conductivities (e.g., aluminum nitride), and/or other suitable thermally conductive materials.
In some embodiments, the first bond material 114a and/or the second bond material 114b can be made from what are known in the art as “thermal bond materials” or “TIMs”, which are designed to increase the thermal contact conductance at surface junctions (e.g., between a die surface and a heat spreader). TIMs can include silicone-based greases, gels, or adhesives that are doped with conductive materials (e.g., carbon nano-tubes, solder materials, diamond-like carbon (DLC), etc.), as well as phase-change materials. In other embodiments, the first bond material 114a and/or the second bond material 114b can include other suitable materials, such as metals (e.g., copper) and/or other suitable thermally conductive materials.
Some or all of the first and/or second semiconductor dies 102 can be at least partially encapsulated in a dielectric underfill material 116. The underfill material 116 can be deposited or otherwise formed around and/or between some or all of the dies to enhance a mechanical connection with a die and/or to provide electrical isolation between conductive features and/or structures (e.g., interconnects). The underfill material 116 can be a non-conductive epoxy paste, a capillary underfill, a non-conductive film, a molded underfill, and/or include other suitable electrically-insulative materials. In several embodiments, the underfill material 116 can be selected based on its thermal conductivity to enhance heat dissipation through the dies of the assembly 100. In some embodiments, the underfill material 116 can be used in lieu the first bond material 114a and/or the second bond material 114b to attach the casing 110 to the top-most first semiconductor die 102a
The semiconductor dies 102 can each be formed from a semiconductor substrate, such as silicon, silicon-on-insulator, compound semiconductor (e.g., Gallium Nitride), or other suitable substrate. The semiconductor substrate can be cut or singulated into semiconductor dies having any of variety of integrate circuit components or functional features, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, other forms of integrated circuit devices, including memory, processing circuits, imaging components, and/or other semiconductor devices. In selected embodiments, the assembly 100 can be configured as a hybrid memory cube (HMC) in which the first semiconductor dies 102a provide data storage (e.g., DRAM dies) and the second semiconductor die 102b provides memory control (e.g., DRAM control) within the HMC. In some embodiments, the assembly 100 can include other semiconductor dies in addition to and/or in lieu of one or more of the semiconductor dies 102. For example, such semiconductor dies can include integrated circuit components other than data storage and/or memory control components. Further, although the assembly 100 includes nine dies stacked on the interposer 120, in other embodiments the assembly 100 can include fewer than nine dies (e.g., six dies) or more than nine dies (e.g., twelve dies, fourteen dies, sixteen dies, thirty-two dies, etc.). For example, in one embodiment, the assembly 100 can include four memory dies stacked on two logic dies. Also, in various embodiments, the semiconductor dies 102 can have different sizes. For example, in some embodiments the second semiconductor die 102b can have the same footprint as at least one of the first semiconductor dies 102a.
As further shown in
The interconnect structures 130 can each include a plurality of redundant electrical connectors 134 (“redundant connectors 134”) coupled between individual first traces 140a and individual second traces 140b of adjacent semiconductor dies 102. As such, each pair of first and second traces 140a and 140b is electrically and thermally coupled together by a plurality of the redundant connectors 134. In one aspect of this embodiment, the redundant connectors 134 can improve process yield during manufacturing. For example, as described in greater detail below, the individual structures 130 are less prone to open circuit relative to conventional interconnects or other electrical connectors because there are a plurality of redundant connectors spaced apart from each other along the traces 140a and 140b. In another aspect of this embodiment, the redundant connectors 134 can enhance thermal conduction through the stack of semiconductor dies 102 and toward the cap portion 112 of the casing 110. In particular, the redundant connectors 134 can provide multiple heat transfer paths between adjacent semiconductor dies 102. In several embodiments, the redundant connectors 134 can be spaced apart from one another along the individual traces 140a and 140b to distribute heat laterally across the semiconductor dies 102. In additional or alternate embodiments, additional redundant electrical connectors 138 (shown in hidden lines) can extend between interior portions (e.g., between the TSVs 142) and/or outer portions (e.g., toward the edges of the dies 102) of the semiconductor dies 102 to further distribute heat.
In general, one challenge with solder bond materials is that they can fail to properly bond an interconnect to a bond pad.
Interconnect structures configured in accordance with several embodiments of the present technology, however, can address these and other limitations of conventional interconnects and related structures. Referring again to
Another advantage of the interconnect structures of the various embodiments is that the redundant electrical connectors can reduce the current density through a conductive joint (e.g., through the bond material 235 of the redundant interconnects 234). For example, an interconnect structure having ten redundant connectors can have about a ten-fold reduction in current density through each of its conductive joints. A related advantage is that the lower current density can reduce electromigration. For example, a lower current density can reduce electromigration through tin/silver-based (SnAg) solder joints, which are typically much more susceptible to electromigration than other interconnect materials (e.g., copper). In some embodiments, the number of redundant electrical connectors can be selected to achieve a certain reduction in electromigration balanced against a potential increase in capacitance across the interconnect structure.
A further advantage of the interconnect structures of the various embodiments is that the redundant electrical connectors can be closely packed.
Any one of the interconnect structures and/or semiconductor die assemblies described above with reference to
From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, although several of the embodiments of the semiconductor dies assemblies are described with respect to HMCs, in other embodiments the semiconductor die assemblies can be configured as other memory devices or other types of stacked die assemblies. In addition, while in the illustrated embodiments certain features or components have been shown as having certain arrangements or configurations, other arrangements and configurations are possible. For example, while the TSV 442 (
This application is a continuation of U.S. patent application Ser. No. 17/183,276, filed Feb. 23, 2021, now U.S. Pat. No. 11,233,036; which is a continuation of U.S. patent application Ser. No. 16/257,438, filed Jan. 25, 2019, now U.S. Pat. No. 10,943,888; which is a continuation of U.S. patent application Ser. No. 15/724,102, filed Oct. 3, 2017, now U.S. Pat. No. 10,192,852; which is a continuation of U.S. patent application Ser. No. 15/162,209, filed May 23, 2016, now U.S. Pat. No. 9,818,728; which is a divisional of U.S. patent application Ser. No. 14/287,418, filed May 27, 2014, now U.S. Pat. No. 9,356,009; each of which is incorporated herein by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
6468894 | Yang et al. | Oct 2002 | B1 |
6841438 | Bissey et al. | Jan 2005 | B2 |
6884707 | Cherian | Apr 2005 | B1 |
7541217 | Chang et al. | Jun 2009 | B1 |
7659612 | Hembree et al. | Feb 2010 | B2 |
7759161 | Tanaka et al. | Jul 2010 | B2 |
7900347 | Rathburn | Mar 2011 | B2 |
7935573 | Mizukoshi | May 2011 | B2 |
8237274 | Rahman | Aug 2012 | B1 |
8330272 | Haba | Dec 2012 | B2 |
8492911 | Bachman et al. | Jul 2013 | B2 |
8525346 | Rathburn | Sep 2013 | B2 |
8558374 | Markovich et al. | Oct 2013 | B2 |
8575954 | Chong et al. | Nov 2013 | B2 |
8610264 | Oganesian et al. | Dec 2013 | B2 |
8686552 | Chow et al. | Apr 2014 | B1 |
8772920 | Thacker et al. | Jul 2014 | B2 |
9000557 | Or-Bach et al. | Apr 2015 | B2 |
9356009 | Chandolu | May 2016 | B2 |
9818728 | Chandolu | Nov 2017 | B2 |
10192852 | Chandolu | Jan 2019 | B2 |
10943888 | Chandolu | Mar 2021 | B2 |
11233036 | Chandolu | Jan 2022 | B2 |
20030063450 | Miller | Apr 2003 | A1 |
20040101663 | Agarwala et al. | May 2004 | A1 |
20060012049 | Lin | Jan 2006 | A1 |
20060014376 | Agarwala et al. | Jan 2006 | A1 |
20060186906 | Bottoms et al. | Aug 2006 | A1 |
20070228549 | Hsu et al. | Oct 2007 | A1 |
20090001602 | Chung | Jan 2009 | A1 |
20090091026 | Fan | Apr 2009 | A1 |
20090243121 | Ito | Oct 2009 | A1 |
20100096760 | Yu et al. | Apr 2010 | A1 |
20110095418 | Lim et al. | Apr 2011 | A1 |
20130037879 | Filippini et al. | Feb 2013 | A1 |
20130069230 | Vodrahalli | Mar 2013 | A1 |
20130134582 | Yu et al. | May 2013 | A1 |
20130292823 | Chapelon et al. | Nov 2013 | A1 |
20150348954 | Chandolu | Dec 2015 | A1 |
20160268235 | Chandolu | Sep 2016 | A1 |
20180026015 | Chandolu | Jan 2018 | A1 |
20190157246 | Chandolu | May 2019 | A1 |
20210202446 | Chandolu | Jul 2021 | A1 |
Number | Date | Country |
---|---|---|
101728371 | Jun 2010 | CN |
2007109746 | Apr 2007 | JP |
2010103533 | May 2010 | JP |
2010161102 | Jul 2010 | JP |
2010251427 | Nov 2010 | JP |
Entry |
---|
CN Patent Application No. 201580036987.5—Chinese Office Action and Search Repod, dated Jun. 20, 2018, with English Translation, 22 pages. |
CN Patent Application No. 201580036987.5—Chinese Office Action, dated Jul. 18, 2019, with English Translation, 20 pages. |
CN Patent Application No. 201580036987.5—Chinese Office Action, dated Mar. 21, 2019, with English Translation, 11 pages. |
EP Patent Application No. 15800355.8—European Office Action, dated Dec. 13, 2019, 4 pages. |
JP Patent Application No. 2016-569053—Japanese Office Action, dated Nov. 28, 2017, with English Translation, 24 pages. |
Korean Patent Application No. 10-2016-7036122—Korean Office Action, dated Nov. 30, 2018, with English Translation, 6 pages. |
Extended European Search Report dated Dec. 22, 2017 in European Application No. 15800355.8, 9 pages. |
International Search Report dated Aug. 27, 2015 in International App. No. PCT/US2015/032216, 18 pages. |
Office Action dated May 10, 2016 in Taiwan Application No. 104117024, 19 pages. |
Office Action dated Feb. 20, 2018 in Korean Application No. 10-2016-7036122, 18 pages. |
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20220149011 A1 | May 2022 | US |
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Parent | 14287418 | May 2014 | US |
Child | 15162209 | US |
Number | Date | Country | |
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Parent | 17183276 | Feb 2021 | US |
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Parent | 16257438 | Jan 2019 | US |
Child | 17183276 | US | |
Parent | 15724102 | Oct 2017 | US |
Child | 16257438 | US | |
Parent | 15162209 | May 2016 | US |
Child | 15724102 | US |