In an aspect of integrated circuit packaging technologies, individual semiconductor dies may formed and are initially isolated. These semiconductor dies may then be bonded together, and the resulting die stack may be connected to other package components such as package substrates (e.g., interposers, printed circuit boards, and the like) using connectors on a bottom die of the die stack.
The resulting packages are known as Three-Dimensional Integrated Circuits (3DICs). Top dies of a die stack may be electrically connected to the other package components through interconnect structures (e.g., through-substrate vias (TSVs)) in bottom dies of the die stack. However, existing 3DIC packages may include numerous limitations. For example, the bonded die stack and other package components may result in a large form factor and may require complex heat dissipation features. Furthermore, existing interconnect structures (e.g., TSVs) of the bottom die may be costly to manufacture and result in long conduction paths (e.g., signal/power paths) to top dies of the die stack.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Various embodiments may include a plurality of first dies (e.g., memory dies) electrically connected to one or more second dies (e.g., logic dies) through first input/output (I/O) pads and redistribution layers (RDLs) formed on the second dies. The resulting die stack may be bonded to another package component such as an interposer, package substrate, printed circuit board, and the like through second I/O pads and the RDLs of the second dies. The package substrate may include a cavity, and the first dies may be disposed in the cavity. Thus, a three-dimensional integrated circuit (3DIC) such as a chip on fan-out package may be made with a relatively small form factor at a relatively low cost and having relatively short conduction paths (e.g., signal/power paths). Furthermore, one or more heat dissipation features may be independently formed on opposite surfaces of the first and/or second dies.
The interconnect layers may include an inter-layer dielectric (ILD)/inter-metal dielectric layers (IMDs) formed over the substrate. The ILD and IMDs may be formed of low-k dielectric materials having k values, for example, lower than about 4.0 or even about 2.8. In some embodiments, the ILD and IMDs comprise silicon oxide, SiCOH, and the like.
A contact layer 12 including one or more contact pads is formed over the interconnect structure and may be electrically coupled to the active devices through various metallic lines and vias in the interconnect layers. Contact pads in contact layer 12 may be made of a metallic material such as aluminum, although other metallic materials may also be used. A passivation layer (not shown) may be formed over contact layer 12 out of non-organic materials such as silicon oxide, un-doped silicate glass, silicon oxynitride, and the like. The passivation layer may extend over and cover edge portions of contact pads in contact layer 12. Openings may be formed in portions of the passivation layer that cover the contact pads, exposing at least a portion of the contact pads in contact layer 12. The various features of dies 10 may be formed by any suitable method and are not described in further detail herein. Furthermore, dies 10 may be formed in a wafer (not shown) and singulated. Functional testing may be performed on dies 10. Thus, dies 10 in
Next, referring to
In
In
Interconnect structures 20 (e.g., conductive lines and/or vias) may be formed in polymer layers 22 and electrically connected to contact layer 12 of dies 10. The formation of interconnect structures 20 may include patterning polymer layers 22 (e.g., using a combination of photolithography and etching processes) and forming interconnect structures 20 (e.g., depositing a seed layer and using a mask layer to define the shape of interconnect structures 20) in the patterned polymer layers 22. Interconnect structures 20 may be formed of copper or a copper alloy although other metals such as aluminum, gold, and the like may also be used. Interconnect structures 20 may be electrically connected to contact pads in contact layer 12 (and as a result, active devices) in dies 10.
Furthermore, connectors 24 and 26 may vary in size. For example, connectors 24 may be microbumps having a pitch of about 40 μm or more while connectors 26 may be controlled collapse chip connection (C4) bumps having a pitch of about 140 μm to about 150 μm. In alternative embodiments, connectors 24 and 26 may include different dimensions. Thus, as illustrated by
The differing sizes of connectors 24 and 26 may allow different electrical devices (e.g., having differently sized connectors) to be bonded to dies 10. For example, connectors 24 may be used to electrically connect dies 10 to one or more other device dies 28 (see
In
Next, as illustrated by
Package substrate 30 may be an interposer, a printed circuit board (PCB), and the like. For example, package substrate 30 may include a core 37 and one or more build-up layers 39 (labeled 39A and 39B) disposed on either side of core 37. Interconnect structures 38 (e.g., conductive lines, vias, and/or through vias) may be included in package substrate 30 to provide functional electrical purposes such as power, ground, and/or signal layers. Other configurations of package substrate 30 may also be used.
Furthermore, package substrate 30 may include a cavity 36. Cavity 36 may not extend through package substrate 30. Rather, a portion or all of build-up layers 39A (e.g., build-up layers 39 disposed on a same side of core 37 as die stack 10/32) may be patterned to form cavity 36. As illustrated in
Package substrate 30 may be formed using any suitable method. For example,
Next, in
As illustrated by
In
Referring back to
Next, referring to
Compared to conventional 3DICs, where package substrate 30 and dies 32 would be disposed on opposing sides of die 10, package 100 provides die 10 with a surface 10′, which may not be used to electrically connect to dies 32 or package substrate 30. Thus, heat dissipation feature 40 may be directly disposed on surface 10′ of die 10 for improved heat dissipation.
Interfacing material 42 may be disposed between heat dissipation features 40 and die 10/molding compound 16. Interfacing material 42 may include a thermal interface material (TIM), for example, a polymer having a good thermal conductivity, which may be between about 3 watts per meter kelvin (W/m·K) to about 5 W/m·K or more. Because the TIM may have good thermal conductivity, the TIM may be disposed directly between (e.g., contacting) die 10 and heat dissipation feature 40. Furthermore, interfacing material 42 may also include an adhesive (e.g., an epoxy, silicon resin, and the like) for affixing heat dissipation lid 40 to die 10/molding compound 16. The adhesive used may have a better adhering ability and a lower thermal conductivity than a TIM. For example, the adhesive used may have a thermal conductivity lower than about 0.5 W/m·K. As such, the adhesive portions of interfacing material 42 may be disposed over areas having lower thermal dissipation needs (e.g., over surfaces of molding compound 16).
After the attachment of heat dissipation feature 40, a marking process (e.g., laser marking) may be performed to mark package 100. Furthermore, as illustrated by
The configuration of package substrate 30 in package 300 may be altered from the configuration in package 100. For example, cavity 36 may be disposed on an opposing side (rather than a same side) of package substrate 30. In package 300, die 10 may be bonded to a surface 30A of package substrate 30. Surface 30A may be substantially level. Package substrate 30 may further include surface 30B (e.g., in cavity 36) and surface 30C opposing die 10. Due to the inclusion of cavity 36, surfaces 30B and 30C may not be substantially level. For example, in the orientation illustrated by
The formation of package substrate 30 having cavity 36 may include the patterning of core 37, build-up layer 39B (e.g., disposed on an opposing side of core 37 as die 10), and/or build-up layer 39A (e.g., disposed on a same side of core 37 as die 10). In various embodiments, cavity 36 may not extend through package substrate 30.
Subsequently, functional tests may be performed on package 300 prior to the attachment of dies 32. For example, electrical connections between die 10 and package substrate 30 may be tested. If package 300 passes the tests, dies 32 may be attached to package 300, for example, using connectors 24 formed as illustrated by
Connectors 24 (e.g., microbumps) may be formed on dies 32 using any suitable method. Connectors 24 may be of a different size than connectors 26, and connectors 24 may be attached to contact pads on package substrate 30. Connectors 24 may be electrically connect dies 32 to die 10 through interconnect structures 38 in package substrate 30 (e.g., interconnect structures 38′), connectors 26, and RDLs 18.
Dies 32 may be disposed in cavity 36 of package substrate. In package 300, dies 32 and die 10 may be disposed on opposing sides of package substrate 30. Attaching dies 32 may include flipping package 300 (e.g., so that connectors 24 face upwards) and aligning dies 32 in cavity 36. A reflow may be performed on connectors 24 (e.g., to electrically connect dies 32 to die 10/package substrate 30), an underfill 34 may be dispensed around connectors 24.
The configuration of package 300 allows for a heat dissipation feature (e.g., heat dissipation feature 70) to be disposed on a surface dies 32. An interfacing material 72 may be disposed between heat dissipation feature 70 and dies 32, and interfacing material 72 may be in physical contact with dies 32. Heat dissipation feature 70 and interfacing material 72 may be substantially similar to heat dissipation feature 40 and interfacing material 42, respectively. Thus, an alternative manufacturing process may be used to form package 300.
Thus, as described above, a package substrate may include a cavity. A first die may be bonded to the package substrate. Where the cavity may be on the same side of the package substrate as the first die or on an opposing side of the package substrate as the first die. One or more second dies may be bonded to the package substrate and the first die, and the second dies may be disposed in the cavity. The second die may be bonded directly to the first die, or the second die may be bonded directly to the package substrate. Thus, the configuration of the package substrate allows for a package having a relatively thin form factor. Furthermore, the configuration of the dies in the package may allow for relatively simplistic heat dissipation elements to be attached to at least the first die.
In accordance with an embodiment, a device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs, and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.
In accordance with another embodiment, a device includes first die, one or more redistribution layers (RDLs) on the first die, a first plurality of connectors on a surface of the one or more RDLs, a plurality of second dies, and a package substrate electrically connected to the first die and the plurality of second dies. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate includes a core, one or more first build-up layers on a first side of the core, and one or more second build-up layers on a second side of the core opposite the first side. The one or more second build-up layers is patterned to form a cavity in the package substrate, and the plurality of second dies is at least partially disposed in the cavity.
In accordance with yet another embodiment, a method includes forming one or more redistribution layers (RDLs) on a first side of a first die, forming first connectors on the one or more redistribution layers, and bonding a package substrate to the first die using the first connectors. The package substrate is electrically connected to the first die through the one or more RDLs, and the package substrate includes a cavity. The method further includes electrically connecting a second die to the package substrate. The second die is at least partially disposed in the cavity.
In accordance with yet another embodiment, a device includes a package substrate. The package substrate includes a metal-clad insulated base material core, the metal-clad insulated base material core having a topmost surface and a bottommost surface opposite the topmost surface, and a cavity extending through the metal-clad insulated base material core. The device further includes a first die at least partially within the cavity and a first plurality of connectors in the cavity. The first plurality of connectors couple the first die to the package substrate. The first plurality of connectors extends below the topmost surface of the metal-clad insulated base material core toward a bottommost surface of the cavity. The first plurality of connectors directly contacts the bottommost surface of the cavity.
In accordance with yet another embodiment, a device includes a package substrate. The package substrate includes: a core, the core having a topmost surface and a bottommost surface opposite the topmost surface; one or more first build-up layers on the topmost surface of the core; one or more second build-up layers on the bottommost surface of the core; and a cavity extending through the one or more first build-up layers and the core. A surface of the one or more second build-up layers exposed by the cavity is substantially level with the bottommost surface of the core. The device further includes a first die extending into the cavity and a first plurality of connectors in the cavity. The first die is bonded to the package substrate through the first plurality of connectors. Portions of the first plurality of connectors extend between the topmost surface of the core and the bottommost surface of the core.
In accordance with yet another embodiment, a method includes forming a package substrate. Forming the package substrate includes forming one or more first build-up layers on a first side of a metal-clad insulated base material core. One or more second build-up layers are formed on a second side of the metal-clad insulated base material core. The second side of the metal-clad insulated base material core is opposite the first side of the metal-clad insulated base material core. A cavity is patterned through the one or more first build-up layers and the metal-clad insulated base material core to expose a surface of the one or more second build-up layers. The method further includes bonding a first die to the package substrate using a first plurality of connectors. The first die is at least partially disposed in the cavity. A sidewall of at least one of the first plurality of connectors faces a sidewall of a portion of the cavity disposed within the metal-clad insulated base material core.
In accordance with yet another embodiment, a method includes forming a package substrate. Forming the package substrate includes forming one or more first build-up layers on a metal-clad insulated base material core. A cavity is formed through the metal-clad insulated base material core to expose a first surface of the one or more first build-up layers. The method further includes attaching a first die to the one or more first build-up layers using a first plurality of connectors. The first plurality of connectors are in physical contact with the first surface of the one or more first build-up layers.
In accordance with yet another embodiment, a method includes forming a package substrate. Forming the package substrate includes forming one or more first build-up layers on a first surface of a metal-clad insulated base material core. The metal-clad insulated base material core is patterned to form a cavity through the metal-clad insulated base material core. The method further includes placing a die stack into the cavity. A die stack is electrically coupled to the package substrate using a first plurality of connectors. Portions of the first plurality of connectors extend between the first surface of the metal-clad insulated base material core and a second surface of the metal-clad insulated base material core. The second surface of the metal-clad insulated base material core is opposite the first surface of the metal-clad insulated base material core.
In accordance with yet another embodiment, a method includes forming a package substrate. Forming the package substrate includes forming one or more first build-up layers on a first side of a metal-clad insulated base material core. One or more second build-up layers are formed on a second side of the metal-clad insulated base material core. The second side of the metal-clad insulated base material core is opposite the first side of the metal-clad insulated base material core. A cavity is patterned through the one or more second build-up layers and the metal-clad insulated base material core to expose a surface of the one or more first build-up layers. The method further includes bonding a first die to the package substrate using a first plurality of connectors. The first die is at least partially disposed in the cavity. A sidewall of at least one of the first plurality of connectors faces a sidewall of a portion of the cavity disposed within the metal-clad insulated base material core.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application is a divisional of U.S. patent application Ser. No. 16/015,791, filed on Jun. 22, 2018, entitled “Substrate Design for Semiconductor Packages and Method of Forming Same,” which is a continuation of U.S. patent application Ser. No. 14/181,305, filed on Feb. 14, 2014, now U.S. Pat. No. 10,056,267, issued Aug. 21, 2018, entitled “Substrate Design for Semiconductor Packages and Method of Forming Same,” which applications are incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
4728751 | Canestaro et al. | Mar 1988 | A |
4811082 | Jacobs et al. | Mar 1989 | A |
4990462 | Sliwa, Jr. | Feb 1991 | A |
5075253 | Sliwa, Jr. | Dec 1991 | A |
5380681 | Hsu | Jan 1995 | A |
5481133 | Hsu | Jan 1996 | A |
5818404 | Lebby et al. | Oct 1998 | A |
5895978 | Palagonia | Apr 1999 | A |
5977640 | Bertin et al. | Nov 1999 | A |
6002177 | Gaynes et al. | Dec 1999 | A |
6025648 | Takahashi et al. | Feb 2000 | A |
6187678 | Gaynes et al. | Feb 2001 | B1 |
6229216 | Ma et al. | May 2001 | B1 |
6236115 | Gaynes et al. | May 2001 | B1 |
6271059 | Bertin et al. | Aug 2001 | B1 |
6271469 | Ma et al. | Aug 2001 | B1 |
6279815 | Correia et al. | Aug 2001 | B1 |
6355501 | Fung et al. | Mar 2002 | B1 |
6434016 | Zeng et al. | Aug 2002 | B2 |
6448661 | Kim et al. | Sep 2002 | B1 |
6461895 | Liang et al. | Oct 2002 | B1 |
6562653 | Ma et al. | May 2003 | B1 |
6570248 | Ahn et al. | May 2003 | B1 |
6600222 | Levardo | Jul 2003 | B1 |
6603072 | Foster et al. | Aug 2003 | B1 |
6607938 | Kwon et al. | Aug 2003 | B2 |
6661085 | Kellar et al. | Dec 2003 | B2 |
6762076 | Kim et al. | Jul 2004 | B2 |
6790748 | Kim et al. | Jul 2004 | B2 |
6791195 | Urushima | Sep 2004 | B2 |
6879041 | Yamamoto et al. | Apr 2005 | B2 |
6879510 | Kang et al. | Apr 2005 | B2 |
6887769 | Kellar et al. | May 2005 | B2 |
6908565 | Kim et al. | Jun 2005 | B2 |
6908785 | Kim | Jun 2005 | B2 |
6921968 | Chung | Jul 2005 | B2 |
6924551 | Rumer et al. | Aug 2005 | B2 |
6943067 | Greenlaw | Sep 2005 | B2 |
6946384 | Kloster et al. | Sep 2005 | B2 |
6975016 | Kellar et al. | Dec 2005 | B2 |
7037804 | Kellar et al. | Jun 2006 | B2 |
7056807 | Kellar et al. | Jun 2006 | B2 |
7087538 | Staines et al. | Aug 2006 | B2 |
7098542 | Hoang et al. | Aug 2006 | B1 |
7151009 | Kim et al. | Dec 2006 | B2 |
7157787 | Kim et al. | Jan 2007 | B2 |
7215033 | Lee et al. | May 2007 | B2 |
7217994 | Zhu et al. | May 2007 | B2 |
7276799 | Lee et al. | Oct 2007 | B2 |
7279795 | Periaman et al. | Oct 2007 | B2 |
7307005 | Kobrinsky et al. | Dec 2007 | B2 |
7317256 | Williams et al. | Jan 2008 | B2 |
7320928 | Kloster et al. | Jan 2008 | B2 |
7345350 | Sinha | Mar 2008 | B2 |
7402442 | Condorelli et al. | Jul 2008 | B2 |
7402515 | Arana et al. | Jul 2008 | B2 |
7410884 | Ramanathan et al. | Aug 2008 | B2 |
7432592 | Shi et al. | Oct 2008 | B2 |
7443030 | Muthukumar et al. | Oct 2008 | B2 |
7494845 | Hwang et al. | Feb 2009 | B2 |
7528494 | Furukawa et al. | May 2009 | B2 |
7531890 | Kim | May 2009 | B2 |
7557597 | Anderson et al. | Jul 2009 | B2 |
7576435 | Chao | Aug 2009 | B2 |
7632719 | Choi et al. | Dec 2009 | B2 |
7659632 | Tsao et al. | Feb 2010 | B2 |
7834450 | Kang | Nov 2010 | B2 |
7928582 | Hutto | Apr 2011 | B2 |
8063654 | Rahman et al. | Nov 2011 | B2 |
8164171 | Lin et al. | Aug 2012 | B2 |
8284561 | Su et al. | Oct 2012 | B2 |
8361842 | Yu et al. | Jan 2013 | B2 |
8519537 | Jeng et al. | Aug 2013 | B2 |
8680647 | Yu et al. | Mar 2014 | B2 |
8703542 | Lin et al. | Apr 2014 | B2 |
8759964 | Pu et al. | Jun 2014 | B2 |
8778738 | Lin et al. | Jul 2014 | B1 |
8785299 | Mao et al. | Jul 2014 | B2 |
8796846 | Lin et al. | Aug 2014 | B2 |
8803306 | Yu et al. | Aug 2014 | B1 |
8803332 | Lee et al. | Aug 2014 | B2 |
8809996 | Chen et al. | Aug 2014 | B2 |
8829676 | Yu et al. | Sep 2014 | B2 |
8865521 | Jeng et al. | Oct 2014 | B2 |
8877554 | Tsai et al. | Nov 2014 | B2 |
8896109 | Pagaila et al. | Nov 2014 | B2 |
8933551 | Chang et al. | Jan 2015 | B2 |
8970023 | Chou et al. | Mar 2015 | B2 |
9129929 | Lundberg | Sep 2015 | B2 |
9202782 | Chuah | Dec 2015 | B2 |
9564416 | Hou et al. | Feb 2017 | B2 |
9653442 | Yu et al. | May 2017 | B2 |
20020003232 | Ahn et al. | Jan 2002 | A1 |
20020003297 | Smola et al. | Jan 2002 | A1 |
20020081755 | Degani et al. | Jun 2002 | A1 |
20030035270 | Shieh et al. | Feb 2003 | A1 |
20040056344 | Ogawa et al. | Mar 2004 | A1 |
20040245608 | Huang et al. | Dec 2004 | A1 |
20050009259 | Farnworth | Jan 2005 | A1 |
20050104196 | Kashiwazaki | May 2005 | A1 |
20060113653 | Xiaoqi et al. | Jun 2006 | A1 |
20060145328 | Hsu | Jul 2006 | A1 |
20060249828 | Hong | Nov 2006 | A1 |
20070196953 | Fasano et al. | Aug 2007 | A1 |
20070289127 | Hurwitz et al. | Dec 2007 | A1 |
20070290319 | Kim | Dec 2007 | A1 |
20080116589 | Sinha | Mar 2008 | A1 |
20080150125 | Braunisch et al. | Jun 2008 | A1 |
20080157316 | Yang | Jul 2008 | A1 |
20080185713 | Dani et al. | Aug 2008 | A1 |
20080185719 | Cablao et al. | Aug 2008 | A1 |
20080248610 | Chew et al. | Oct 2008 | A1 |
20080265434 | Kurita | Nov 2008 | A1 |
20080272477 | Do et al. | Nov 2008 | A1 |
20080283992 | Palaniappan et al. | Nov 2008 | A1 |
20080315372 | Kuan et al. | Dec 2008 | A1 |
20090065927 | Meyer | Mar 2009 | A1 |
20090121326 | Kim et al. | May 2009 | A1 |
20090186446 | Kwon et al. | Jul 2009 | A1 |
20090230409 | Basin et al. | Sep 2009 | A1 |
20090230531 | Do et al. | Sep 2009 | A1 |
20090243065 | Sugino et al. | Oct 2009 | A1 |
20090309212 | Shim et al. | Dec 2009 | A1 |
20090321921 | Hwang | Dec 2009 | A1 |
20100019370 | Pressel et al. | Jan 2010 | A1 |
20100052135 | Shim et al. | Mar 2010 | A1 |
20100102428 | Lee et al. | Apr 2010 | A1 |
20100244219 | Pagaila et al. | Sep 2010 | A1 |
20100244223 | Cho | Sep 2010 | A1 |
20100276787 | Yu et al. | Nov 2010 | A1 |
20100289134 | Chow | Nov 2010 | A1 |
20100314749 | Kurita | Dec 2010 | A1 |
20100327419 | Muthukumar | Dec 2010 | A1 |
20110024888 | Pagaila et al. | Feb 2011 | A1 |
20110068444 | Chi et al. | Mar 2011 | A1 |
20110068459 | Pagaila et al. | Mar 2011 | A1 |
20110193221 | Hu et al. | Aug 2011 | A1 |
20110210444 | Jeng et al. | Sep 2011 | A1 |
20110241192 | Ding et al. | Oct 2011 | A1 |
20110278732 | Yu et al. | Nov 2011 | A1 |
20110285005 | Lin et al. | Nov 2011 | A1 |
20110291288 | Wu et al. | Dec 2011 | A1 |
20110304999 | Yu et al. | Dec 2011 | A1 |
20120018885 | Lee | Jan 2012 | A1 |
20120049352 | Kang et al. | Mar 2012 | A1 |
20120286407 | Choi et al. | Nov 2012 | A1 |
20130026468 | Yoshimuta et al. | Jan 2013 | A1 |
20130062760 | Hung et al. | Mar 2013 | A1 |
20130062761 | Lin et al. | Mar 2013 | A1 |
20130075903 | Pagaila et al. | Mar 2013 | A1 |
20130082364 | Wang et al. | Apr 2013 | A1 |
20130093097 | Yu et al. | Apr 2013 | A1 |
20130119533 | Chen et al. | May 2013 | A1 |
20130168848 | Lin et al. | Jul 2013 | A1 |
20130182402 | Chen et al. | Jul 2013 | A1 |
20130200529 | Lin et al. | Aug 2013 | A1 |
20130203215 | Hung et al. | Aug 2013 | A1 |
20130214426 | Zhao et al. | Aug 2013 | A1 |
20130249532 | Lin et al. | Sep 2013 | A1 |
20130252378 | Jeng et al. | Sep 2013 | A1 |
20130307140 | Huang et al. | Nov 2013 | A1 |
20140084441 | Chiu | Mar 2014 | A1 |
20140091473 | Len et al. | Apr 2014 | A1 |
20140131858 | Pan et al. | May 2014 | A1 |
20140203429 | Yu et al. | Jul 2014 | A1 |
20140210101 | Lin et al. | Jul 2014 | A1 |
20140217610 | Jeng et al. | Aug 2014 | A1 |
20140225222 | Yu et al. | Aug 2014 | A1 |
20140252646 | Hung et al. | Sep 2014 | A1 |
20140252647 | Huang et al. | Sep 2014 | A1 |
20140264930 | Yu et al. | Sep 2014 | A1 |
20140353823 | Park et al. | Dec 2014 | A1 |
20150061149 | Lin et al. | Mar 2015 | A1 |
20150091131 | Lamorey | Apr 2015 | A1 |
20150187743 | Yu | Jul 2015 | A1 |
20150235915 | Liang et al. | Aug 2015 | A1 |
20150235936 | Yu et al. | Aug 2015 | A1 |
20150235989 | Yu et al. | Aug 2015 | A1 |
20150235990 | Cheng et al. | Aug 2015 | A1 |
20150235993 | Cheng et al. | Aug 2015 | A1 |
20160240508 | Hou et al. | Aug 2016 | A1 |
20170229432 | Lin et al. | Aug 2017 | A1 |
20170338177 | Lin et al. | Nov 2017 | A1 |
20170345788 | Pan et al. | Nov 2017 | A1 |
Number | Date | Country |
---|---|---|
202394961 | Aug 2012 | CN |
202523706 | Nov 2012 | CN |
2008103536 | May 2008 | JP |
4339309 | Oct 2009 | JP |
20090028687 | Mar 2009 | KR |
20090122277 | Nov 2009 | KR |
20100119507 | Nov 2010 | KR |
20120019091 | Mar 2012 | KR |
20130077031 | Jul 2013 | KR |
Entry |
---|
Kurita, Yoichiro et al., “SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory”, Innovative Common Technologies to Support State-of-the-Art Products, 2006, pp. 52-56. |
Kurita, Yoichiro et al., “SMAFTI Packaging Technology for New Interconnect Hierarchy”, IEEE International Interconnect Technology Conference, Jun. 1-3, 2009, pp. 220-222. |
Motohashi, N. et al., “SMAFTI Package with Planarized Multilayer Interconnects”, IEEE, Electronic Components and Technology Conference, 2009, pp. 599-606. |
Ranganathan, N., et al., “Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon Interconnection,” 58th Electronic Components and Technology Conference, ECTC 2008, May 2008, pp. 859-865, IEEE, Lake Buena Vista, Florida, United States. |
Number | Date | Country | |
---|---|---|---|
20200013635 A1 | Jan 2020 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 16015791 | Jun 2018 | US |
Child | 16573064 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14181305 | Feb 2014 | US |
Child | 16015791 | US |