Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

GPHYSICS G11Information storage G11CSTATIC STORES

G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

G11C29/003in serial memories G11C29/006at wafer scale level G11C29/02Detection or location of defective auxiliary circuits G11C29/021in voltage or current generators G11C29/022in I/O circuitry G11C29/023in clock generator or timing circuitry G11C29/024in decoders G11C29/025in signal lines G11C29/026in sense amplifiers G11C29/027in fuses G11C29/028with adaption or trimming of parameters G11C29/04Detection or location of defective memory elements G11C29/06Acceleration testing G11C29/08Functional testing G11C29/10Test algorithms G11C29/12Built-in arrangements for testing G11C29/12005comprising voltage or current generators G11C29/1201comprising I/O circuitry G11C29/12015comprising clock generation or timing circuitry G11C29/14Implementation of control logic G11C29/16using microprogrammed units G11C29/18Address generation devices Devices for accessing memories G11C29/20using counters or linear-feedback shift registers [LFSR] G11C29/22Accessing serial memories G11C29/24Accessing extra cells G11C29/26Accessing multiple arrays G11C29/28Dependent multiple arrays G11C29/30Accessing single arrays G11C29/32Serial access Scan testing G11C29/34Accessing multiple bits simultaneously G11C29/36Data generation devices G11C29/38Response verification devices G11C29/40using compression techniques G11C29/42using error correcting codes [ECC] or parity check G11C29/44Indication or identification of errors G11C29/4401for self repair G11C29/46Test trigger logic G11C29/48Arrangements in static stores specially adapted for testing by means external to the store G11C29/50Marginal testing G11C29/50004of threshold voltage G11C29/50008of impedance G11C29/50012of timing G11C29/50016of retention G11C29/52Protection of memory contents Detection of errors in memory contents G11C29/54Arrangements for designing test circuits G11C29/56External testing equipment for static stores G11C29/56004Pattern generation G11C29/56008Error analysis, representation of errors G11C29/56012Timing aspects, clock generation, synchronisation G11C29/56016Apparatus features G11C29/70Masking faults in memories by using spares or by reconfiguring G11C29/702by replacing auxiliary circuits G11C29/72with optimized replacement algorithms G11C29/74using duplex memories G11C29/76using address translation or modifications G11C29/765in solid state disks G11C29/78using programmable devices G11C29/781combined in a redundant decoder G11C29/783with refresh of replacement cells G11C29/785with redundancy programming schemes G11C29/787using a fuse hierarchy G11C29/789using non-volatile cells or latches G11C29/80with improved layout G11C29/802by encoding redundancy signals G11C29/804to prevent clustered faults G11C29/806by reducing size of decoders G11C29/808using a flexible replacement scheme G11C29/81using a hierarchical redundancy scheme G11C29/812using a reduced amount of fuses G11C29/814for optimized yield G11C29/816for an application-specific layout G11C29/818for dual-port memories G11C29/82for EEPROMs G11C29/822for read only memories G11C29/824for synchronous memories G11C29/83with reduced power consumption G11C29/832with disconnection of faulty elements G11C29/835with roll call arrangements for redundant substitutions G11C29/838with substitution of defective spares G11C29/84with improved access time or stability G11C29/842by introducing a delay in a signal path G11C29/844by splitting the decoders in stages G11C29/846by choosing redundant lines at an output stage G11C29/848by adjacent switching G11C29/86in serial access memories G11C29/88with partially good memories G11C29/883using a single defective memory device with reduced capacity G11C29/886combining plural defective memory devices to provide a contiguous address range