SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING

Abstract

Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body.

Description

BACKGROUND OF THE INVENTION

FIGS. 1A-1H show simplified cross-sectional views of a conventional process for fabricating a package for a semiconductor device. The views of FIGS. 1A-H are simplified in that the relative proportions of the various components are not shown to the scale.

In FIG. 1A, a planar, continuous rolls 102 of conducting material such as copper, is provided.

In FIG. 1B, material is removed from regions of the planar roll 102 utilizing a chemical etching process. This chemical etching process involves forming a mask, and then etching in regions exposed by the mask, followed by removal of the mask. This chemical etching serves to define a central diepad 104 surrounded by a metal matrix 106. Although not shown in the particular cross-sectional view in FIG. 1B, portions of the diepad 104 may remain integral with the metal matrix 106.

FIG. 1C shows partial etching of the backside of portions of the patterned roll 102. Etched regions 104a of the periphery of the diepad 104 will later serve to allow the diepad to be physically secured within the plastic molding of the package body. Etched regions 108a correspond to portions of pins of the lead frame. These etched regions 108a will later serve to allow the pins to be physically secured within the plastic molding of the package body. FIG. 1C marks the step of completion of formation of lead frame 103.

FIG. 1D shows the formation of an electrically conducting adhesive material 110 on the die attach region 104b of the diepad 104. This electrically conducting adhesive material maybe comprise soft solder deposited in molten form. Alternatively, the electrically conducting adhesive material may comprise solder paste that is deposited in the form of small-sized particles of solder in a binder such as a solvent.

FIG. 1E shows the die-attach step, wherein the back side 112a of semiconductor die 112 is placed against electrically conducting adhesive material 110. As shown in FIG. 1E, one consequence of this die attach step may be the spreading of material 110 on the diepad 104 beyond the perimeter of the die 112.

FIG. 1F shows a subsequent step, wherein bond wires 114 are attached between contacts on the top surface 112b of the die 112 and pins 108.

FIG. 1G shows a further subsequent step, wherein the diepad 104, die 112, bond wires 114, and portions of the pins 108 are encapsulated with a plastic molding material 116 to define a body 118 of the package. As previously indicated, the recesses 104a and 108a serve to physically secure the diepad and pins, respectively, within the package during this encapsulation step.

FIG. 1H shows a subsequent singulation step, wherein the package 120 is separated from the surrounding metal frame by a sawing process.

While the conventional process flow just described is adequate to form a semiconductor device package, it may offer certain drawbacks. In particular, the partial etching step shown in FIG. 1C may be difficult to achieve, and hence adds to the cost of manufacturing the device. In particular, this partial etching step involves a number of steps, including the highly accurate patterning of a mask, followed by only partial etching in exposed areas and then removal of the mask. In particular, the partial etching of the metal roll may be difficult to halt with sufficient accuracy and repeatability.

Accordingly, there is a need in the art for a process for forming a semiconductor device package which avoids the need for a partial etching step.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body.

According to one embodiment, a semiconductor device package is provided. The semiconductor device package includes a die and a plurality of terminals configured to be in electrical communication with the die through one or more bond structures. Each of the plurality of terminals includes a first portion extruding from the device package and a second portion disposed outside a plane of the first portion and having stamped feature at an edge of the second portion. The stamped feature extends laterally beyond the edge of the second portion and is thinner than the edge of the second portion. The semiconductor device package further includes a package body encapsulating the die, the one or more bond structures, and the second portion of each of the plurality of terminals.

According to another embodiment, a method for manufacturing a semiconductor device package is provided. The method includes providing a die, providing a lead frame with a plurality of terminals configured to be in electrical communication with the die through one or more bond structures, and stamping the plurality of terminals to form, for each of the terminals (1) a first portion of the terminal that is displaced along a certain dimension in relation to a second portion of the terminal, the first portion of the terminal being electrically connected with the second portion of the terminal via a connecting portion, and (2) a stamped feature at an edge of the first portion of the terminal. The stamped feature extends laterally beyond the edge of the first portion of the terminal and is thinner than the edge of the first portion of the terminal. The method further includes encapsulating the die, the one or more bond structures, and the first portion of each of the plurality of terminals in a package body.

According to yet another embodiment an integrated circuit package is provided. The integrated circuit package includes a die having a plurality of electrical contacts disposed along a surface of the die, and a plurality of terminals configured to be in electrical communication with the die. Each of the plurality of terminals includes one or more bond structures electrically connecting the terminal with one or more of the plurality of electrical contacts, a first portion extruding from the device package, and a second portion disposed outside a plane of the first portion and having stamped feature at an edge of the second portion. The stamped feature extends laterally beyond a part of the second portion that is not stamped and is thinner than the part of the second portion that is not stamped. The integrated circuit package also includes a package body encapsulating the die, the one or more bond structures, and the second portion of each of the plurality of terminals.

These and other embodiments of the present invention, as well as its features and some potential advantages are described in more detail in conjunction with the text below and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-H show simplified cross-sectional views of a conventional process for fabricating a package.

FIGS. 2A-2K show simplified cross-sectional views of an embodiment of a process in accordance with the present invention for forming a package.

FIGS. 2CA-2CC show end views of various complex cross-sectional profiles that may be imparted by stamping according to embodiments of the present invention.

FIG. 3 shows a simplified view of the flow of a process according to an embodiment of the present invention.

FIG. 4A shows a simplified perspective view of the lead frame of an embodiment of a package in accordance with the present invention housing three die.

FIG. 4B is a simplified plan view showing the die and bond structures of the package of FIG. 4A.

FIG. 5 is a simplified plan view showing a lead frame according to another embodiment of the present invention.

FIG. 5A is a simplified cross-sectional view taken along the line A-A′ of FIG. 5.

FIG. 5B is a simplified plan view showing positioning of a die and bond wires on the lead frame of FIG. 5.

FIG. 6 is a simplified plan view showing a lead frame according to yet another embodiment of the present invention.

FIG. 6A is a simplified cross-sectional view taken along the line A-A′ of FIG. 6.

FIG. 7A is a simplified cross-sectional view of another embodiment of a lead frame of the present invention.

FIG. 7B shows an enlarged plan view of a portion of the lead frame of FIG. 7A.

FIG. 7C shows an enlarged cross-sectional view of the lead frame of FIG. 7B taken along line C-C′.

FIG. 8 is a simplified illustration of a power QFN (P-QFN) semiconductor device package, according to one embodiment.

FIG. 9 is a simplified illustration of a lead frame and die that can be utilized in a semiconductor device package, according to one embodiment.

FIGS. 10 and 11 are simplified cross-sectional profiles of device packages, such as the P-QFN of FIG. 8, utilizing a configurable lead frame similar to the lead frame discussed in relation to FIG. 9.

FIG. 12 is a simplified flowchart illustrating a method for manufacturing a semiconductor device package according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention relate to the formation of semiconductor device packages utilizing stamping. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, the pins of a package may be imbued with a chamfered or other complex cross-sectional profile by a stamping process. Other techniques, employed alone or in combination, may facilitate fabrication of a package by stamping.

FIGS. 2A-2K show simplified cross-sectional views of a process in accordance with an embodiment of the present invention for forming a semiconductor device package. The views of FIGS. 2A-2K are simplified in that the relative proportions of the components of the package are not shown to scale.

In FIG. 2A, a planar, continuous roll 202 of conducting material such as copper, is provided. In particular embodiments, the metal roll may have a thickness of between about 4-20 mils (0.004″-0.020″). In certain embodiments, the metal roll has a thickness of between about 6-10 mils (0.006″-0.010″).

In FIG. 2B, material is removed from the planar roll 202 utilizing a punching process, with points of removal of material indicated by the triangles. This punching process serves to define a central diepad 204 surrounded by a metal matrix 206. Although not shown in the particular cross-sectional view in FIG. 2B, portions of the diepad 204 may remain integral with the surrounding metal matrix 206.

Also defined during the punching step of FIG. 2B are a plurality of pins 208 integral with the surrounding metal matrix. According to certain embodiments, the minimum width of these pins is about 0.15 mm, and the minimum pitch between the pins is about 0.4 mm, where the pitch is defined as the distance between the center lines of adjacent pins. In particular embodiments where the thickness of the metal roll is between about 6-10 mils, the width of these pins is about 0.25 mm and the pitch between the pins is about 0.5 mm.

FIG. 2B shows that the lateral dimension (A′) of the diepad 204, may be slightly smaller than the corresponding lateral dimension (A) of the diepad 104 formed by the conventional process shown in FIG. 1B. As discussed in detail below, this smaller diepad size may be a result of fabrication of the package utilizing stamping techniques.

Specifically, FIG. 2C shows the use of stamping to impart several features to the lead frame. One feature formed by stamping is an indentation at the edge of the diepad and/or pins. Specifically, FIG. 2C shows indentation 204a around the periphery of the underside of diepad 204. FIG. 2C also shows indentation 208a at the edge of the pin. proximate to the diepad. By receiving the plastic molding of the package body during the subsequent encapsulation step, stamped indentations 204a and 208a serve to enhance mechanical interlocking between the body of the package and the diepad and pins respectively.

Another lead frame feature shown in FIG. 2C formed by stamping, is elevation of a portion 208b of pins 208 above a horizontal plane of the diepad 204. This raising of portions 208b of the pins 208 closest to the diepad 204, causes the pins to penetrate deeper into the body of the package, helping to physically secure the pins within the encapsulating plastic mold of the package body. Raising of the pin portions also relieves stress in the bond structure, by making the ends of the bond structure located at approximately the same height.

According to certain embodiments, the stamping process may raise the pin portions 208a to a height Z above the surface of the diepad 204, where Z corresponds approximately to an expected thickness of a die supported on the diepad, and a conducting adhesive material between the die and the diepad.

Still another feature which may be imparted to a lead frame during the stamping of FIG. 2C, is a complex cross-sectional profile to a middle portion 208c of the pin 208. Specifically, FIG. 2CA shows a view of middle portion 208b of the pin 208, taken along section A-A′ of FIG. 2C. FIG. 2CB shows a view of a portion of the pin 208 taken g section B-B of FIG. 2C.

In the particular embodiment of FIGS. 2CA-CB, the middle pin portion 208b exhibits a chamfered profile, with sides positioned at an angle relative to the vertical disposition of the sides of the other portions of the pin. In this embodiment, the complex cross-sectional profiles imparted to the lead frame by stamping according to embodiments of the present invention, enhances mechanical interlocking of the pins within the plastic body of the package. In addition, the stamped cross-sections allow the pins to offer a larger surface area to the surrounding molding material, thereby further enhancing mechanical interlocking between lead frame and package body. Moreover, the complex stamped cross-sectional profiles may allow the pins to better relieve physical stress during the subsequent singulation step, thus avoiding damage at the interface between the pin and the plastic package body.

While FIG. 2CA shows the complex cross-sectional profile as being a chamfer, this is not required by the present invention. In other embodiments, the cross-sectional profile imparted by stamping could be hour-glass shaped, T-shaped, H-shaped, angled or curved concave or convex, or saw tooth shaped, as shown in FIG. 2CC.

The various features formed by stamping in FIG. 2C need not be created in a single stamping step. One or more separate stamping impacts under different conditions could be employed to create the stamped features.

FIG. 2D shows a simplified view of a post-stamping electroplating process according to an embodiment of the present invention. Specifically, electroplated material 222 is selectively formed on certain regions of the lead frame.

Specifically, electroplated material 222 may be formed on the die attach portion 204b of the diepad 204 that is expected to receive the die. Where the die to be supported by the diepad has an electrical contact on its lower surface (such as the drain of a MOSFET), the electroplated material 222 will likely contain silver (Ag).

Another location of electroplated material is at an end of the elevated portion 208a of the pin 208 proximate to the diepad 204. As discussed in detail below, these electroplated regions are expected to receive the electrically conducting bond wire, bond ribbon, or bond clip from the top surface of the supported die.

The composition of the electroplated material 222 may be dictated by the composition of the bond wire/ribbon/clip with which the electroplated material will be in contact. The following TABLE provides a listing of electroplated materials under different conditions.

	TABLE
	Bonding	Material	Finished Lead Surface for Bonding
	Wire	Gold Wire	Ni, Ag, Ni/Au, or Ni/Pd/Au
		Al-Wire	Bare Cu, Ni, Ag, Ni/Au, or Ni/Pd/Au
		Cu-wire	Bare Cu, Ni, Ni/Au, or Ni/Pd/Au
	Ribbon	Al	Bare Cu, Ni, Ag, Ni/Au, or Ni/Pd/Au
		Cu-	Bare Cu, Ni, Ni/Au, or Ni/Pd/Au
	Clip	Cu	Bare Cu, Ni, Ni/Au, or Ni/Pd/Au

FIG. 2E shows a next step in the process, wherein the electroplated lead frame is exposed to an oxidizing ambient 224. As a result of this exposure, portions of the lead frame that have not been electroplated, become oxidized and form “brown oxide” 226. As discussed below, this brown oxide 226 may exhibit properties that are useful in subsequent steps in the package. In particular, formation of a brown oxide guard band 226a circumscribing the die attach area 204b, may be useful.

FIG. 2F shows the next step, wherein die 212 is provided having its lower surface 212a already coated with an electrically conducting adhesive material 210 such as soft solder. This step obviates the need for the selective deposition of the electrically conducting adhesive material on the die attach area that is shown in FIG. 1D of the convention process.

FIG. 2G shows the next step, wherein die 212 bearing electrically conducting adhesive material 210, is placed against die attach area 204a of diepad 204. In this step, the presence of the brown oxide guard band 226, secures to restrain the flow of the soft solder material beyond the confines of the die attach area. Specifically, the roughness and non-wetting properties of the brown oxide inhibit the spreading of the soft solder.

During the package singulation process shown in FIG. 2K, the pins 208 are exposed to significant physical strain as the punching blade moves through the metal. However, during this slicing process the angled edges offered by the chamfered cross-sectional profile of the pin shown in FIG. 2CA, serves to enhance mechanical interlocking of the pins within the plastic body material, and reduce physical strain at the interface between the pins and the package body.

The package singulation process in FIG. 2K leaves package 220 having exposed surface 208d of pin portions 208 and exposed surface 204d of diepad 204 stripped of brown oxide and ready for soldering to an underlying printed circuit (PC) board (not shown).

While the particular embodiment shown above depicts fabrication of a package housing a single die, the present invention is not limited to such a package. Alternative embodiments in accordance with the present invention could be used to form packages housing two, three, or even larger numbers of die.

FIG. 3 shows a simplified flow diagram of a process for fabricating a package according to an embodiment of the present invention. In a first step 302 of process 300, a continuous planar roll of conducting material is provided.

In a second step 304 of process 300, holes are punched completely through to remove material from the metal role and thereby define the pattern of the diepad and pins.

In a third step 306, the patterned metal roll is subjected to one or more stamping processes to create features on the pin and diepad portions of the package. As discussed in detail above, examples of such features include indentations on the underside of the diepad, pin portions exhibiting a chamfered cross-sectional profile, and raised pin portions.

In a fourth step 308, portions of the lead frame may optionally be electroplated with an appropriate metal. Examples of such electroplated regions include the die attach area, and the raised portions of the pins that are expected to receive an end of a bond structure such as a wire, ribbon, or clip having its other end in contact with the die.

In a fifth step 310, the stamped lead frame is exposed to an oxidizing ambient. A result of this exposure to the oxidizing ambient is the formation of brown oxide on all exposed portions of the lead frame surface. As discussed previously, this oxidation may desirably lead to the formation of an oxide guard band circumscribing the die attach area.

In a sixth step 312, brown oxide on the bottom surface of the pins and diepad may be removed. In certain embodiments, this oxide removal may be accomplished by physically lapping the bottom of the lead frame. In other embodiments, this oxide removal may be accomplished by exposure to a chemical etching environment.

The oxide removal step may occur immediately following the oxidation step, as indicated in FIG. 3. In other embodiments, however, the oxide removal step may occur later in the process, for example following the encapsulation step.

In a seventh step 314, the die is attached to the die attach area. In certain embodiments, this die attach step may include prior application of an electrically conducting adhesive material to the die attach area of the diepad. Alternative embodiments may utilize a die having its back side already coated with the electrically conducting adhesive material.

In an eighth step 316, the appropriate bonding structure(s) are attached between the surface of the die and the appropriate pin, which may be electroplated. As discussed above, the bond structure may be a conducting clip, wire, or ribbon.

In a ninth step 318, the die, bond structure, and portions of the pins and diepad are encapsulated within a plastic molding material to form the body of the package.

During this step, the diepad and pins remain fixed to the surrounding metal matrix of the original metal roll.

In a tenth step 320, the individual package is singulated from the surrounding metal matrix by punching through the metal. During this singulation process, a chamfered or other complex cross-sectional profile imparted to the pins by stamping, may enhance mechanical interlocking of the pins within the package body, and allow the pins to relieve physical stress resulting from the shearing of the metal.

In additional steps (not shown), the package may be attached to an underlying PC board utilizing solder. The previous removal of brown oxide by lapping may facilitate the performance of this step.

The process described above represents only one particular embodiment of the present invention. Other embodiments may omit certain steps, include additional steps, or perform the steps in a specific order other than that indicated.

For example, the selective electroplating step is not required, and according to certain embodiments the bonding structure may be in contact with the bare metal of the roll rather than an electroplated feature. Moreover, the use of a bonding clip is not required by the present invention and certain embodiments could employ only bonding ribbons or wires to establish electrical connection with contact(s) on the top of the die.

Embodiments in accordance with the present invention offer a number of possible advantages over conventional package fabrication processes. In particular, by avoiding the need for complex and difficult-to-achieve steps of forming raised/recessed features on the lead frame by marking and partial etching, embodiments in accordance with the present invention offer cost savings.

Comparison of FIGS. 1B and 2B indicates that one characteristic that may not be offered by embodiments of the present invention, is a larger diepad area available to support a larger die. Specifically, features on the lead frame are formed by stamping that does not completely remove the material of the metal roll. Thus, in order to maintain the same lateral spacing B between the diepad and pins as in the etched package, embodiments of the present invention may utilize a diepad having slightly reduced dimensions (A′ vs. A) in order to accommodate the stamped metal.

However, various other aspects of processes according to embodiments of the present invention may serve to offset any smaller size of the diepad and die. For example, the formation of the brown oxide guard band circumscribing the die attach area, effectively constrains the flow of the electrically conducting adhesive material during the die attach process. This in turn allows reduction in the peripheral area of the diepad that must be allocated to avoid the flowed material from undesirably affecting regions outside the die attach area.

Moreover, certain embodiments involve the use of clips instead of bond wires. Such use of a bond clip may allow for a reduced resistance electrical connection between the die contacts and the surrounding pins. This may in turn permit the use of a smaller die having performance comparable to a larger one.

Similarly, the use of selective electroplating may also offer a reduced resistance electrical connection between the die contacts and the surrounding pins. Again, this offers the possibility of a smaller die exhibiting performance comparable to a larger die.

The above figures present an exemplary embodiment only, and the present invention is not limited by this particular embodiment. For example, while the above figures show a diepad having indented features formed by stamping, this is not required by the present invention. According to other embodiments, a diepad could have raised features formed by stamping, such as raised features on a periphery of the diepad.

Moreover, while the specific embodiment shown above includes pin portions proximate to the diepad that are elevated by stamping, the present invention is not limited to this approach. In accordance with alternative embodiments, portions of the pins distal from the diepad could be inclined downward by stamping, thereby offering an embodiment wherein the bottom of the diepad is not exposed following encapsulation of the package body.

In addition, while the above figures describe an embodiment of a package configured to house a single die, this is not required by the present invention. Alternative embodiments of packages according to the present invention can be configured to house two or more die.

For example, FIGS. 4A-B show different views of an embodiment of a quad flat no-lead (QFN) package housing three different die. Specifically, FIG. 4A shows a perspective view of the lead frame 403 only of the QFN package. FIG. 4B shows a plan view of the entire package 420 of FIG. 4A, including the die housed therein and the bonding structures attached thereto, with the outline of the plastic package body shown.

The lead frame 403 of the particular embodiment of FIGS. 4A-4B is formed from a copper roll having a thickness of between about 6-10 mils. The pins 408 have a width of about 0.25 mm or greater. The pitch between the pins is about 0.5 mm or greater.

Specifically, the stamped end frame 403 of package 420 comprises three diepads 404, 407, and 409, respectively supporting first MOSFET die 412, second MOSFET die 455, and integrated circuit (IC) die 460. Diepad 404 is the largest of the three, having an elongated die attach area 404a configured to support MOSFET die 412.

The pins of the package offer contact with three discrete portions of the first MOSFET die 412. Specifically, ganged pin nos. 21-27 are in low resistance communication with the source contact located on the top surface of the die 412, through clips 450. Pins 16, 20, and 28-31 are integral with the diepad 404, and hence offer a low resistance electrical communication with the drain of the MOSFET through a contact in the bottom surface of the die. The gate of the MOSFET is in electrical communication with a contact of the integrated circuit (IC) die 409 through bond wire 452.

Similarly, the pins of the package 420 offer contact with three discrete portions of the second MOSFET die 455. Specifically, ganged pin nos. 34-36 are in low resistance communication with the source contact located on the top surface of the die 455, through bonding clips 450. Pins 1-2, 4, and 33 are integral with the diepad 407, and hence offer a low resistance electrical communication with the drain of the MOSFET through a contact in the bottom surface of the die. The gate of the MOSFET is in electrical communication with pin 3 through bond wire 452.

Unlike the MOSFET die just described, the IC die 460 features a large number of contacts on its top surface. These various contacts are in electrical communication with the following pin nos.: 5, 7-9, 11-13, 15, and 17-18.

IC die 460 may or may not have an electrical contact in its lower surface. If it does, pins 6, 10, and 14 integral with the diepad 409 provide for low electrical resistance communication with that underside contact.

The multi-die embodiment of the QFN package 420 of FIGS. 4A-4B includes the stamped features of the single die package. Specifically, the diepads include indentations 404a, 407a, and 409a respectively as shown in dashed lines. These indentations are formed by stamping, and help to provide mechanical interlocking of the diepads with the encapsulant of the plastic mold material.

Another feature of the multi-die embodiment of the QFN package 420 of FIGS. 4A-4B is the chamfered cross-sectional profile 408c of portions of the pins 408 lying just inside the plastic package body. As described above, these chamfered cross-sectional profiles serves to enhance mechanical interlocking with the surrounding molding of the package body, and increase the amount of surface area of the pin in contact with the plastic molding. In addition, the angled orientation of the sides of the pins serves to reduce stress within the package during punching at the time of singulation.

Yet another feature of the multi-die embodiment of the QFN package 420 of FIGS. 4A-4B is the raising of portions of the pins above the horizontal plane of the diepad. Specifically, during fabrication portions of the pins are bent by stamping to impart them with an inclined portion 408a and a corresponding raised portion 408b proximate to the diepads. As previously indicated, such a profile helps to ensure that the pins remain securely embedded within the plastic molding of the package. The raised pin profile also serves to ease strain in the bonding structure, by placing the surface of the pin at the height of the top surface of the die expected to be supported by the diepad.

As previously indicated, the multi-die embodiment of the QFN package 420 includes an IC die which may or may not have an electrical contact on its back side. Such an IC die would not be expected to generate as much heat as other dies such as MOSFETs. Accordingly, an epoxy die attach film may be used to adhere the IC die to the diepad. Such an epoxy film may be formed as a solid, and would not be expected to flow or spread during the die attach step. Accordingly, for embodiments of the present invention where a package is fabricated housing only an IC die, formation of a brown oxide guard band followed by lapping, may not be necessary.

While the embodiments described above illustrate the use of stamping to impart a chamfered cross-sectional profile to pin portions, this particular cross-sectional profile is not required by embodiments of the present invention. According to alternative embodiments, stamping could imbue pins with other cross-sectional profiles and remain with the scope of the invention. Examples of such other cross-sectional profiles include but are not limited to hourglass shaped, angled or curved concave, angled or curved convex, or saw tooth.

During conventional package fabrication processes, the diepad may be secured to the surrounding metal of the roll utilizing tie-bar structures. These conventional tie-bar structures stabilize the diepad during die attach, and encapsulation steps, and are then severed during the package singulation.

One advantage of embodiments in accordance with the present invention, is the dispensing of the need for a tie-bar structure. Specifically, the embodiment of FIGS. 4A-B does not include tie-bars or severed portions thereof. In particular, prior to the singulation step, each diepad is connected to a surrounding metal frame by way of at least two non-integral pins that would be integral with surrounding portions of the metal matrix. These integral pin portions function in the role of a tie-bar, physically stabilizing the diepad and insuring the physical integrity of the lead frame prior to the singulation step.

The absence of tie-bars offer a number of advantages. One advantage is having more area in the corners of a package to place more pins. Another advantage is that there is no exposed part of tie bars on a surface of a package.

While the embodiment of FIG. 4B shows a lead frame lacking tie-bars and including ganged groups of non-integral pins for communicating with non-IC die, this is not required by the present invention. FIG. 5 is a simplified plan view showing a lead frame according to another embodiment of the present invention, and FIG. 5A is a simplified cross-sectional view taken along the line A-A′ of FIG. 5.

The embodiment of FIGS. 5-5A shows a lead frame 500 having tie-bars 502 integral at the corners of the diepad 506. Coined indents 508 located on the underside of the diepad 506 are configured to interlock with plastic molding of the package upon encapsulation.

FIG. 5B is a simplified plan view showing positioning of a die and bond wires on the lead frame of FIG. 5. As shown in FIG. 5B, the large number of exclusively single individual pins 510 of this embodiment, are suitable for communicating through bond wires with the plurality of contacts present on a top surface of a complex IC die such as a microprocessor, that is supported on the diepad.

Types of features other than those explicitly described above, can be formed on a lead frame by coining according to alternative embodiments of the present invention. For example, FIG. 6 is a simplified plan view showing a lead frame according to yet another embodiment of the present invention, supporting a die. FIG. 6A is a simplified cross-sectional view taken along the line A-A′ of FIG. 6, absent the die.

The embodiment of FIGS. 6-6A shows a lead frame 600 which includes a number of holes 602 formed by stamping or coining, in the periphery of the diepad region 604. The holes 602 allow penetration of plastic molding during the encapsulation step, thereby providing additional mechanical interlocking of the lead frame.

In addition, the holes 602 serve to isolate and preserve rim/runway area 606 (from the die to the edge of the die-pad) for down bonding. In particular the presence of the holes serves to contain unwanted bleeding or overflow of die attach material during the die attach step. For example, in one embodiment where the diepad has an overall width of 5.1 mm, the hole may have a width of 0.2 mm, and may be separated from the diepad edge by a distance of 0.2 mm forming the down bond runway.

Lead frames according to embodiments of the present invention may combine multiple features that are formed by coining. For example, the lead frame shown in FIGS. 6A-B features both the coined holes, and pins having elevated portions and cross-sectional profiles formed by coining.

As a further example of a lead frame having multiple coined features, FIG. 7A is a simplified cross-sectional view of another embodiment of a lead frame of the present invention. FIG. 7B shows an enlarged plan view of a portion of the lead frame of FIG. 7A including a supported die. FIG. 7C shows an enlarged cross-sectional view of the lead frame of FIG. 7B taken along line C-C′, including a supported die.

Specifically, the lead frame 700 of the embodiments of FIGS. 7A-C includes both a coined indent 702 on the underside of the periphery of the diepad, and a plurality of holes 704 formed by coining in the periphery of the diepad region. The location of holes 704 define a down bond runway region 706 that is configured to receive a down bond wire from the supported die, and which is shielded from overflow of die attach material by the holes.

FIGS. 8-11 are simplified diagrams illustrating how stamped features and/or heatsinks may be implemented in certain embodiments of the present invention. Referring to a FIG. 8, a simplified diagram is provided illustrating a bottom view 801, a top view 802, and side views 803, 804 of a Power QFN (P-QFN) package 800, according to one embodiment. The package 800 includes a series of pins 810, or leads, that provide electrical connectivity to a die (not shown) encapsulated inside.

According to the embodiment illustrated in FIG. 8, a heatsink 820 may be provided. The heatsink 820 can be embedded in and/or exposed by an surface of the package 800 and thermally coupled to the die to help conduct heat away from the die encapsulated inside the package 800. A further description of how a heatsink can be utilized is provided in U.S. patent application Ser. No. 12/186,342, entitled “SEMICONDUCTOR PACKAGE FEATURING FLIP-CHIP DIE SANDWICHED BETWEEN METAL LAYERS,” the entirety of which is incorporated by reference for all purposes.

FIG. 9 is a simplified illustration of a lead frame 903 and die 900 that can be utilized with various embodiments, including the package 800 of FIG. 8. Among various other features, the lead frame 903 can include a first portion 920 that includes a plurality of pins 922 that can protrude from the device package to provide electrical connection to the die 900. (It is noted that FIG. 9 shows an additional portion on the opposite side of the lead frame that is not labeled.) Depending on the desired configuration of the device package and/or die 900, different pins 922 may be connected to a single terminal. In the embodiment of FIG. 9, for example, the lead frame 903 includes four terminals: two having three pins each, and the other two having only a single pin each.

The lead frame can also include a second portion 930 internal to the device package that includes stamped features 932. These stamped features 932, which can be located at the edges of the terminals, can be formed by stamping and/or coining the lead frame. The stamping and/or coining can flatten portions of the lead frame, causing the stamped features 932 to be thinner than the other edges of the terminals that are not stamped and/or coined, and extend laterally beyond the edges of the terminals that are not stamped and/or coined. Such stamped features 932 can help the terminals interlock with the package body and hold them in place. To this end, the stamped features 932 also can include patterns and/or profiles (including complex cross-sectional profiles) that may further help the terminals interlock with the package body.

The lead frame can also include a third portion 910 internal to the device package that includes a plurality of fingers 912 configured to support and/or provide electrical connection to the die 900. The configuration of the fingers (e.g., size, length, number, etc.) can vary, depending on desired functionality. For example, the configuration of FIG. 9 shows a first terminal with three fingers 912-1, a second terminal with two fingers 912-2, and the remaining two terminals with one finger each 912-3. Other embodiments may have more or less terminals with more or less fingers 912. Additionally, the fingers 912 of two or more terminals may be interdigitated, as shown in FIG. 9.

FIG. 9 additionally shows front 901 and side 902 views of the die 900, which illustrate how the die 900 can have a plurality of contacts 940 that correlate to the fingers 912 of the lead frame 903. The configurability of the fingers 912 and/or contacts 940 can accommodate a wide number of applications. In general, the contacts 940 can be a series of parallel, electrically-conducting columns, separated by a certain distance 970, configured to be electrically connected with the fingers of the lead frame, which are correspondingly aligned with the columns. According to some embodiments, for example, one or more columns may be split, thereby forming multiple contacts with can be connected to different terminals. For example, FIG. 9 illustrates a column having two contacts 940-1 configured to contact two corresponding fingers 912-3 of the lead frame 903. Such a configuration not only can allow for multiple types of die to utilize a single type of lead frame 903 in a flip-chip configuration without the need for a diepad or additional connectors connecting the contacts 940 on the die 900 to the terminals of the lead frame. Of course, different lead frames can have differently-patterned fingers 912 to accommodate any number of contact 940 configurations on the die 900.

The fingers 912 and/or contacts 940 can include bond structures to help ensure a good electrical connection between the fingers 912 and contacts 940. Such bond structures can include, for example, a land pattern, ball grid array (BGA), gold and/or copper pillar, and the like. A person of ordinary skill in the art will recognize numerous alterations, substitutions, and variations.

FIGS. 10 and 11 are simplified cross-sectional profiles of device packages, such as the P-QFN 800 of FIG. 8, utilizing a configurable lead frame similar to the lead frame discussed in relation to FIG. 9. Referring to FIG. 10, for example, a device package 1015 is shown having a die 1000 and a heatsink 1080. The device package 1015 further includes a lead frame having a first portion 1020, a second portion 1030, and a third portion corresponding to respective first, second, and third portions 920, 930, 910 of the lead frame 903 of FIG. 9.

The lead frame of the device package 1015 further illustrates how embodiments can include a connecting portion 1050 that includes stamped feature that connects the first portion 1020 to the second portion 1030. (Note that, for clarity, only one of the two connecting portions 1050 of FIG. 10 are labeled.) According to one embodiment, for example lead frame of the device package 1015 is provided as one or more substantially flat and/or planar pieces, then the first portion 1020, the second portion 1030, or both is stamped such that the second portion 1030 extends outside a plane of the first portion 1020. Such stamping may not only elevate (or lower) the second portion 1030 above the first portion 1020 to create the connecting portion 1050, but stamping may also be used to create notches, facets, and/or other features in the first portion 1020, second portion 1030, and/or connecting portion 1050 that may help the terminals mechanically interlock with the package body. Such features can cause the portions of the terminals to have complex cross-sectional profiles.

As with other embodiments provided herein, the device package 1015 further illustrates how fingers 1012 can be connected to the contacts of the die 1000 via bond structures 1035. Again, bond structures can include one or more of a variety of structures configured to help ensure a good electrical connection between the fingers 1012 and contacts of the die 1000.

FIG. 11 illustrates yet another embodiment of a device package 1017, similar to the device package 1015 illustrated in FIG. 10. The device package 1017 of FIG. 11, however, does not include a heatsink.

FIG. 12 is a simplified flowchart illustrating a method for manufacturing a semiconductor device package according to an embodiment of the present invention. The method includes providing a die (1210). The method also includes providing a lead frame with a plurality of terminals configured to be in electrical communication with the die through one or more bond structures (1220). The bond structures may be provided on the contacts of the die, on the plurality of terminals (e.g., on fingers of the terminals), or both, depending manufacturing and other concerns.

The method further includes stamping the plurality of terminals to form a first portion displaced along a certain dimension in relation to a second portion, and a stamped feature at an edge of the first portion (1230). As described above, the first portion of the terminals can be stamped such that the first portion is raised above a plane of a second portion (i.e., the portion that protrudes from the package body). The first and second portions of the terminal can be connected via a connecting portion. As explained above, the stamped feature at the edge of the first portion can extend laterally beyond an edge of the first portion of the terminal and is thinner than the edge of the first portion of the terminal. Additionally, as described elsewhere herein, the first, second, and/or connecting portions may include other stamped features to help the terminals mechanically interlock with a package body. Finally, the method includes encapsulating the die, the one or more bond structures, and the first portion of each of the plurality of terminals in a package body (1240). The package body can comprise one or more insulating materials, such as plastic.

It should be appreciated that the specific steps illustrated in FIG. 12 provide a particular method of fabricating an edge termination structure according to an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Moreover, the individual steps illustrated in FIG. 12 may include multiple sub-steps that may be performed in various sequences as appropriate to the individual step. Furthermore, additional steps may be added or removed depending on the particular applications. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

It can be noted that, while many embodiments described in reference to FIGS. 8-12 discuss a P-QFN device package, the invention is not so limited. The techniques and principles discussed may be extended to a wide variety of other integrated circuit package types.

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Claims

1. A semiconductor device package comprising: a die;a plurality of terminals configured to be in electrical communication with the die through one or more bond structures, wherein each of the plurality of terminals includes: a first portion extruding from the device package;a second portion disposed outside a plane of the first portion and having stamped feature at an edge of the second portion, wherein the stamped feature: extends laterally beyond the edge of the second portion; andis thinner than the edge of the second portion; anda package body encapsulating: the die,the one or more bond structures, andthe second portion of each of the plurality of terminals.

2. The semiconductor device package of claim 1 wherein: the plurality of terminals comprise one or more fingers supporting the die; andthe one or more bond structures electrically connect the one or more fingers to the die.

3. The semiconductor device package of claim 1 wherein at least one of the plurality of terminals further comprises one or more pins extruding from the package body.

4. The semiconductor device package of claim 1 wherein each of the plurality of terminals includes comprises a complex cross-sectional profile that mechanically interlocks at least one pin within the package body.

5. The semiconductor device package of claim 1 wherein the stamped feature comprises a first stamped feature, wherein each of the plurality of terminals further comprises a second stamped feature connecting the first portion to the second portion.

6. The semiconductor device package of claim 1 wherein the one or more bond structures comprises at least one of: a land pattern,a ball grid array (BGA),a gold pillar, ora copper pillar.

7. A method for manufacturing a semiconductor device package, the method comprising: providing a die;providing a lead frame with a plurality of terminals configured to be in electrical communication with the die through one or more bond structures;stamping the plurality of terminals to form, for each of the terminals: a first portion of the terminal that is displaced along a certain dimension in relation to a second portion of the terminal, the first portion of the terminal being electrically connected with the second portion of the terminal via a connecting portion; anda stamped feature at an edge of the first portion of the terminal, wherein the stamped feature: extends laterally beyond the edge of the first portion of the terminal; andis thinner than the edge of the first portion of the terminal; andencapsulating the die, the one or more bond structures, and the first portion of each of the plurality of terminals in a package body.

8. The method of claim 7 wherein: forming the plurality of terminals includes forming one or more fingers; andthe one or more bond structures electrically connect the one or more fingers to the die.

9. The method of claim 7 wherein at least one terminal includes more than one pin that protrudes from the package body.

10. The method of claim 7 wherein stamping the plurality of terminals further includes forming, for each of the plurality of terminals, a complex cross-sectional profile that mechanically interlocks at least one pin within the package body.

11. The method of claim 10 wherein the second portion of the terminal comprises the complex cross-sectional profile.

12. The method of claim 7 wherein the one or more bond structures comprises at least one of: a land pattern,a ball grid array (BGA),a gold pillar, ora copper pillar.

13. The method of claim 7 wherein the packaged comprises a power QFN package.

14. An integrated circuit package comprising: a die having a plurality of electrical contacts disposed along a surface of the die;a plurality of terminals configured to be in electrical communication with the die, wherein each of the plurality of terminals includes: one or more bond structures electrically connecting the terminal with one or more of the plurality of electrical contacts;a first portion extruding from the device package;a second portion disposed outside a plane of the first portion and having stamped feature at an edge of the second portion, wherein the stamped feature: extends laterally beyond a part of the second portion that is not stamped; andis thinner than the part of the second portion that is not stamped; anda package body encapsulating: the die,the one or more bond structures, andthe second portion of each of the plurality of terminals.

15. The integrated circuit package of claim 14 wherein: the plurality of terminals comprise one or more fingers supporting the die; andthe one or more bond structures electrically connect the one or more fingers to the die.

16. The integrated circuit package of claim 14 wherein at least one terminal comprises a plurality of pins extruding from the package body.

17. The integrated circuit package of claim 14 wherein each of the plurality of terminals includes comprises a complex cross-sectional profile that mechanically interlocks at least one terminal within the package body.

18. The integrated circuit package of claim 14 wherein the stamped feature comprises a first stamped feature, wherein each of the plurality of terminals further comprises a second stamped feature connecting the first portion to the second portion.

19. The integrated circuit package of claim 14 wherein the one or more bond structures comprises at least one of: a land pattern,a ball grid array (BGA),a gold pillar, ora copper pillar.

20. The integrated circuit package of claim 14 wherein the packaged comprises a power QFN package.